- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377397 > IDT72103L50J (INTEGRATED DEVICE TECHNOLOGY INC) CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 PDF資料下載
參數(shù)資料
| 型號(hào)： | IDT72103L50J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 |
| 中文描述： | 2K X 9 OTHER FIFO, 50 ns, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 7/31頁 |
| 文件大?。?/td> | 314K |
| 代理商： | IDT72103L50J |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
5.37
7
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5.0V
±
10%, T
A
= 0
°
C to +70
°
C)
Commercial
IDT72103L35
IDT72104L35
Min.
IDT72103L50
IDT72104L50
Min.
Timing
Unit
Symbol
DEPTH EXPANSION MODE TIMINGS
t
XOL
Read/Write to
XO
LOW
t
XOH
Read/Write to
XO
HIGH
t
XI
XI
Pulse Width
t
XIR
XI
Recovery Time
t
XIS
XI
Set-up Time
SERIAL-INPUT MODE TIMINGS
t
S2
Serial Data In Set-up Time to SICP Rising Edge
t
H2
Serial Data In Hold Time to SICP Rising Edge
t
S3
SIX Set-up Time to SICP Rising Edge
t
S4
W
Set-up Time to SICP Rising Edge
t
H4
W
Hold Time to SICP Rising Edge
t
SICW
Serial In Clock Width High/Low
t
S5
SI/PI Set-up Time to SICP Rising Edge
SERIAL-OUTPUT MODE TIMINGS
t
S6
SO/PO Set-up Time to SOCP Rising Edge
t
S7
SOX Set-up Time to SOCP Rising Edge
t
S8
R
Set-up Time to SOCP Rising Edge
t
H8
R
Hold Time to SOCP Rising Edge
t
SOCW
Serial Out Clock Width HIGH/LOW
SERIAL MODE RECOVERY TIMINGS
t
REFSO
Recovery Time SOCP after
EF
Goes HIGH
t
RFFSI
Recovery Time SICP after
FF
Goes HIGH
SERIAL MODE FLAG TIMINGS
t
SOCEF
SOCP Rising Edge (Bit 0- Last Word) to
EF
LOW
t
SOCFF
SOCP Rising Edge (Bit 0- First Word) to
FF
HIGH
t
SOCF
SOCP Rising Edge to
FF-1
,
HF
,
AEF
HIGH
t
SOCF
SOCP Rising Edge to
AEF
,
EF
,
EF+1
LOW
t
SICEF
SICP Rising Edge (Last Bit-First Word) to
EF
HIGH
t
SICFF
SICP Rising Edge (Bit 1-Last Word) to
FF
LOW
t
SICF
SICP Rising Edge to
EF+1
,
AEF
HIGH
t
SICF
SICP Rising Edge to
FF-1
,
HF
,
AEF
HIGH
SERIAL-INPUT MODE TIMINGS
t
PD1
SICP Rising Edge to D
(1)
SERIAL-OUTPUT MODE TIMINGS
t
PD2
SOCP Rising Edge to Q
(1)
t
SOHZ
SOCP Rising Edge to SO at High-Z
(1)
t
SOLZ
SOCP Rising Edge to SO at Low-Z
(1)
t
SOPD
SOCP Rising Edge to Valid Data on SO
OUTPUT ENABLE/DISABLE TIMINGS
t
OEHZ
Output Enable to High-Z (Disable)
(1)
t
OELZ
Output Enable to Low-Z (Enable)
(1)
t
AOE
Output Enable to Data Valid (Q
0-8
)
NOTE:
2753 tbl 09
1. Values guaranteed by design, not tested.
Parameter
Max.
Max.
Figure
—
—
35
10
15
35
35
—
—
—
—
—
50
10
15
50
50
—
—
—
ns
ns
ns
ns
ns
13
13
14
14
14
12
0
5
5
7
8
35
—
—
—
—
—
—
—
15
0
5
5
7
10
50
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
19
19
19
19
19
19
19
35
5
5
7
8
—
—
—
—
—
50
5
5
7
10
—
—
—
—
—
ns
ns
ns
ns
ns
20
20
20
20
20
35
15
—
—
80
15
—
—
ns
ns
22
23
—
—
—
—
—
—
—
—
20
30
30
30
45
30
45
45
—
—
—
—
—
—
—
—
25
40
40
40
65
40
65
65
ns
ns
ns
ns
ns
ns
ns
ns
22
24
24,26
22,26
21
23
21,25
23,25
5
17
5
20
ns
17,19
5
5
5
—
17
16
22
18
5
5
5
—
20
16
22
18
ns
ns
ns
ns
20
20
20
20
—
5
—
16
—
20
—
5
—
16
—
22
ns
ns
ns
12
12
12
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72104L50J | CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 |
| IDT72105 | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| IDT72105L25SO | Current-Mode PWM Controller 14-SOIC -40 to 85 |
| IDT72105L25TP | Current-Mode PWM Controller 8-SOIC -40 to 85 |
| IDT72115L25SO | TRANS PNP HF 40VCEO 1.5A TO-126 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72103S50P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72104S120P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72104S50D | 制造商:Integrated Device Technology Inc 功能描述: 制造商:Integrated Device Technology Inc 功能描述:4K X 9 OTHER FIFO, 50 ns, CDIP40 |
| IDT72104S50P | 制造商:IDT/89'S 功能描述:FIFO, 4K x 9, Asynchronous, 40 Pin, Plastic, DIP |
| IDT72105L50S0 | 制造商:Integrated Device Technology Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。