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| 型號(hào)： | IDT72103L50J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 |
| 中文描述： | 2K X 9 OTHER FIFO, 50 ns, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 6/31頁(yè) |
| 文件大?。?/td> | 314K |
| 代理商： | IDT72103L50J |
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5.37
6
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5.0V
±
10%, T
A
= 0
°
C to +70
°
C)
Commercial
IDT72103L35
IDT72104L35
Min.
—
—
—
IDT72103L50
IDT72104L50
Min.
—
—
—
Timing
Unit
MHz
MHz
MHz
Symbol
f
S
f
SOCP
f
SICP
PARALLEL-OUTPUT MODE TIMINGS
t
A
Access Time
t
RR
Read Recovery Time
t
RPW
Read Pulse Width
t
RC
Read Cycle Time
t
WLZ
Write Pulse LOW to Data Bus at Low-Z
(1)
t
RLZ
Read Pulse LOW to Data Bus at Low-Z
(1)
t
RHZ
Read Pulse HIGH to Data Bus at High-Z
(1)
t
DV
Data Valid from Read Pulse HIGH
PARALLEL-INPUT MODE TIMINGS
t
DS
Data Set-up Time
t
DH
Data Hold Time
t
WC
Write Cycle Time
t
WPW
Write Pulse Width
t
WR
Write Recovery Time
RESET TIMINGS
t
RSC
Reset Cycle Time
t
RS
Reset Pulse Width
t
RSS
Reset Set-up Time
t
RSR
Reset Recovery Time
RESET TO FLAG TIMINGS
t
RSF1
Reset to
EF
,
AEF
, and
EF+1
LOW
t
RSF2
Reset to
HF
,
FF
, and
FF-1
LOW
RESET TO OUTPUT TIMINGS – SERIAL MODE ONLY
t
RSQL
Reset Going LOW to Q
0-8
LOW
t
RSQH
Reset Going HIGH to Q
0-8
HIGH
t
RSDL
Reset Going LOW to D
0-8
LOW
RETRANSMIT TIMINGS
t
RTC
Retransmit Cycle Time
t
RT
Retransmit Pulse Width
t
RTS
Retransmit Set-up Time
t
RTR
Retransmit Recovery Time
t
RTF
Retransmit to Flags
PARALLEL MODE FLAG TIMINGS
t
REF
Read LOW to
EF
LOW
t
RFF
Read HIGH to
FF
HIGH
t
RF
Read HIGH to Transitioning
HF
,
AEF
and
FF-1
t
RE
Read LOW to
EF+1
LOW
t
RPE
Read Pulse Width after
EF
HIGH
t
WEF
Write HIGH to
EF
HIGH
t
WFF
Write LOW to
FF
LOW
t
WF
Write LOW to Transitioning
HF
,
AEF
and
FF-1
t
WE
Write HIGH to
EF+1
HIGH
t
WPF
Write Pulse Width after
FF
HIGH
NOTE:
1. Values guaranteed by design, not tested.
Parameter
Max.
22.2
50
50
Max.
15
40
40
Figure
—
—
—
Parallel Shift Frequency
Serial-Out Shift Frequency
Serial-In Shift Frequency
—
10
35
45
5
5
—
5
35
—
—
—
—
—
20
—
—
15
50
65
15
10
—
5
50
—
—
—
—
—
30
—
ns
ns
ns
ns
ns
ns
ns
ns
4
4
4
4
15
4
4
4
18
0
45
35
10
—
—
—
—
—
20
0
50
40
10
—
—
—
—
—
ns
ns
ns
ns
ns
3
3
3
3
3
45
35
35
10
—
—
—
—
50
40
40
10
—
—
—
—
ns
ns
ns
ns
2,18
2,18
2,18
2,17,18
—
—
45
45
—
—
65
65
ns
ns
2
2
20
20
20
—
—
—
20
20
20
—
—
—
ns
ns
ns
18
18
17
45
35
35
10
—
—
—
—
—
35
50
40
40
10
—
—
—
—
—
50
ns
ns
ns
ns
ns
5
5
5
5
5
—
—
—
—
35
—
—
—
—
35
30
30
45
45
—
30
30
45
45
—
—
—
—
—
40
—
—
—
—
40
45
45
65
65
—
45
45
65
65
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
7
8,9,10
11
15
6
7
8,9,10
11
16
2753 tbl 08
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72104L50J | CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 |
| IDT72105 | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| IDT72105L25SO | Current-Mode PWM Controller 14-SOIC -40 to 85 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72103S50P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72104S120P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72104S50D | 制造商:Integrated Device Technology Inc 功能描述: 制造商:Integrated Device Technology Inc 功能描述:4K X 9 OTHER FIFO, 50 ns, CDIP40 |
| IDT72104S50P | 制造商:IDT/89'S 功能描述:FIFO, 4K x 9, Asynchronous, 40 Pin, Plastic, DIP |
| IDT72105L50S0 | 制造商:Integrated Device Technology Inc 功能描述: |
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