參數(shù)資料
型號(hào): IDT72103L50J
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): DRAM
英文描述: CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
中文描述: 2K X 9 OTHER FIFO, 50 ns, PQCC44
封裝: PLASTIC, LCC-44
文件頁(yè)數(shù): 14/31頁(yè)
文件大?。?/td> 314K
代理商: IDT72103L50J
5.37
14
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
COMMERCIAL TEMPERATURE RANGES
SERIAL TIMINGS:
2753 drw 20
RS
t
RS
t
RSS
SICP
0
i-1
i
0
i
t
RSR
(1)
(1)
SICP
t
PD1
t
RSDL
D
0
D
1-8
t
PD1
NOTE:
1. SICP should be in the steady LOW or HIGH during t
RSS
. The first LOW-HIGH (or HIGH-LOW) transition can begin after t
RSR
.
Figure 17. Reset Timings for Serial-In Mode
2753 drw 21
RS
t
RS
t
RSS
SOCP
t
RSR
(1)
(1)
SOCP
t
RSQL
Q
0-8
t
RSC
t
RSQH
NOTE:
1. SOCP should be in the steady LOW or HIGH during t
RSS
. The first LOW-HIGH (or HIGH-LOW) transition can begin after t
RSR
.
igure 18. Reset Timings for Serial-Out Mode
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