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參數(shù)資料
| 型號(hào)： | IDT72103L50J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 |
| 中文描述： | 2K X 9 OTHER FIFO, 50 ns, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 16/31頁 |
| 文件大小： | 314K |
| 代理商： | IDT72103L50J |
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5.37
16
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
COMMERCIAL TEMPERATURE RANGES
2753 drw 24
SICP
t
SICEF
FIRST
SERIAL-IN WORD
SECOND
SERIAL-IN WORD
THIRD
SERIAL-IN
WORD
0
1
n – 1
0
1
n – 1
t
PD1
R
EF
0
EF+1
D
n-1
=W
(2)
t
SICF
t
RE
(3)
(1)
t
REF
NOTES:
1. Parallel Read shown for reference only. Can also use serial output mode.
2. The Empty Flag is de-asserted after the N–1 rising edge of SICP of the first serial-in word. In the Serial-Out mode, a new read operation can begin
t
REFSO
after
EF
goes HIGH. In the Parallel-Out mode, a new read operation can occur immedately after
FF
goes HIGH.
3. The
EF+1
Flag is de-asserted after the N–1 rising edge of SICP of the second serial-in word.
Figure 21. Empty Flag and Empty+1 Flag De-assertion in the Serial-ln Mode
2753 drw 25
SOCP
SERIAL
WORD B
LAST SERIAL
WORD
0
1
t
SOCF
W
EF+1
R=Q
n-1
t
SOCEF
n-2
n-1
0
1
n-2
n-1
0
1
n-2
n-1
0
1
t
REFSO
(2)
(3)
t
WEF
WORD
A
WORD
B
THIRD
WORD
(1)
EF
SERIAL
WORD A
NOTES:
1. Parallel write shown for reference only. Can also use serial input mode.
2. The Empty Flag (
EF
) is asserted in Serial-Out mode by using the t
SOCEF
parameter. This parameter is measured in the worst case condition from the
rising edge of the SOCP used to clock data bit 0. Whenever
EF
goes LOW, there is only one word to be shifted out. In the Parallel-ln mode, the
EF
flag is de-asserted by the rising edge of W. In the Serial-ln mode, the
EF
flag is de-asserted by the rising edge of
W
.
3. First Write rising edge after
EF
is set.
4. Once
EF
has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until
EF
goes HIGH.
Figure 22. Empty Flag and Empty+1 Flag Assertion in the Serial-Out Mode (FIFO Being Emptied)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72104L50J | CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 |
| IDT72105 | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| IDT72105L25SO | Current-Mode PWM Controller 14-SOIC -40 to 85 |
| IDT72105L25TP | Current-Mode PWM Controller 8-SOIC -40 to 85 |
| IDT72115L25SO | TRANS PNP HF 40VCEO 1.5A TO-126 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72103S50P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72104S120P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72104S50D | 制造商:Integrated Device Technology Inc 功能描述: 制造商:Integrated Device Technology Inc 功能描述:4K X 9 OTHER FIFO, 50 ns, CDIP40 |
| IDT72104S50P | 制造商:IDT/89'S 功能描述:FIFO, 4K x 9, Asynchronous, 40 Pin, Plastic, DIP |
| IDT72105L50S0 | 制造商:Integrated Device Technology Inc 功能描述: |
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