參數(shù)資料
型號(hào): IDT72103L50J
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
中文描述: 2K X 9 OTHER FIFO, 50 ns, PQCC44
封裝: PLASTIC, LCC-44
文件頁(yè)數(shù): 29/31頁(yè)
文件大小: 314K
代理商: IDT72103L50J
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
5.37
29
DELAYED
TIMING
GENERATOR
MUX
SERIAL-OUT
REGISTER
9
R
SOCP-SERIAL
OUTPUT CLOCK
PARALLEL-OUT DATA/
TIMED OUTPUT Q
SERIAL-
OUTPUT
DATA
(SO)
0-8
SO/PO
CONTROL
CIRCUIT
SO/PO
OUTPUT FROM
RAM ARRAY
2753 drw 41
9
Figure 38. Serial-Output Circuitry
2753 drw 42
SOCP
V
CC
0
Q OF FIFO #1
AND SOX OF
FIFO #2
SOCP
SOX
SERIAL-OUTPUT
CLOCK
GND
R
Q
8
SO
FIFO #1
1
7
8
9
10
14
15
0
Q OF FIFO #2
AND R OF FIFO
#1 AND FIFO #2
SOCP
SOX
SO
SI/PI
SO/PO
V
CC
GND
SI/PI
SO/PO
V
CC
D
0-8
R
Q
6
9
7
FIFO #2
SERIAL-OUT
DATA
D
0-6
PARALLEL DATA IN
16-BITS WIDE
NOTE:
1. The parallel Data In is tied to D0-8 of FIFO #1 and D0-6 of FIFO #2.
Figure 39. Serial-Output for 16-Bit Parallel Data In
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