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參數(shù)資料
| 型號： | IDT77155L155 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS |
| 中文描述： | 物理層（增距鏡TC - PMD）的用戶網(wǎng)絡接口的155Mbps的ATM網(wǎng)絡中的應用 |
| 文件頁數(shù)： | 13/50頁 |
| 文件大?。?/td> | 307K |
| 代理商： | IDT77155L155 |
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IIDT77155
155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION
Commercial Temperature Range
8.03
13
The outgoing path BIP-8 error detection code (B3) is
calculated over all bits of Synchronous Payload Envelope
(SPE) of STS-3c or STS-1 frame before scrambling by bit
interleaved parity calculation using even parity. The calcu-
lated BIP-8 code is then inserted to the B3 byte of the next
outgoing frame before scrambling. Corrupted BIP-8 code
may be inserted via control register for diagnostic.
The C2 byte is set as “13h” by default for ATM mapping.
Value of C2 may be set by control register via microprocessor.
The Path FEBE can be inserted by accumulating detected
B3 BIP-8 errors from receive direction into FEBE code of the
path status byte (G1) for transmit STS-3c or STS-1 frame.
Path FEBE may be inserted via control register for diagnostic
information.
The Path Remote Defect Indication (RDI) may be set for
outgoing data stream by inserting “1” into bit 5 of path status
byte (G1).
H4 can be inserted by the value, which indicates the offset
between H4 byte position and the ATM cell boundary of the
first cell at the same row.
Synchronous Payload Envelope (SPE) can be mapped
into outgoing STS-3c or STS-1 frame according to the gener-
ating pointer.
TRANSMIT UTOPIA CELL FIFO
The ATM Scrambler scrambles the out going 48 byte cell
payload only (header is not scrambled) by using polynomial
x
43
+ 1. The scrambling function may be disabled.
The Idle Cell Generator Block inserts idle/unassigned
cells into the transmit cell stream if a complete ATM cell was
not written into the transmit FIFO. The GFC, PTI and CLP
may be set via control registers. The “all-zero” pattern is
inserted into the VCI/VPI of header. HEC of the idle cell is
calculated and inserted.
The HEC Generator calculates the CRC-8 code over the
first four byte of header and inserts the CRC-8 code into the
fifth byte of header. The polynomial x
8
+ x
2
+ x + 1 for HEC
generation is used. The coset polynomial x
6
+ x
4
+ x
2
+ 1 is
added to the residue. A 19-bit saturating transmit cell
counter is provided for ATM cell performacne monitoring.
The four serial GFC bits are inserted according to the
framing pulse of the transmit cell. The value of GFC bits may
be set by the control registers.
The Transmit FIFO has four ATM cells depth. It provides
FIFO management and the separation of STS-3c or STS-1
timing from ATM layer timing.
The FIFO management functions are to fill the transmit
four cells FIFO and indicate when cells are ready to be written
into the transmit FIFO and to detect FIFO overflow condition.
When the transmit FIFO contains four cells and the upstream
device still writes cell into FIFO, the overflow condition will be
indicated. A maskable interrupt and status register also
active for overflow condition. The write signal and all data
writing into FIFO are ignored until there is a space in FIFO.
MICROPROCESSOR INTERFACE
The Microprocessor Interface provides interface logic
circuit and the registers for the functions of configuration,
monitoring, control and test.
Figure 1. Cell Delineation State Diagram
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| IDT77155 | PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS |
| IDT77155L155PX | PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS |
| IDT77301 | UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO |
| IDT77301L12PF | UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO |
| IDT77301L12PFI | UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT77155L155PX | 制造商:INT_DEV_TECH 功能描述: |
| IDT77201L25PF | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT77211L155PQF | 制造商:Integrated Device Technology Inc 功能描述:ATM/SONET SEGMENTATION AND REASSEMBLY CIRCUIT, 208 Pin, Plastic, QFP |
| IDT77V011L155DA | 功能描述:INTERFACE DPI-UTOPIA 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| IDT77V011L155DA8 | 功能描述:INTERFACE DPI-UTOPIA 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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