參數(shù)資料
型號： IDT77155L155
廠商： Integrated Device Technology, Inc.
英文描述： PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
中文描述： 物理層（增距鏡TC - PMD）的用戶網(wǎng)絡(luò)接口的155Mbps的ATM網(wǎng)絡(luò)中的應(yīng)用
文件頁數(shù)： 7/50頁
文件大?。?/td> 307K
代理商： IDT77155L155
IIDT77155
155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION
Commercial Temperature Range
8.03
7
Symbol
TFPO
Name
Transmit Framing
Position Output
I/O
O
Description
Transmit frame pulse is an 8 KHz signal synchronized to TCLK. It is pulsed high for one
clock every 2430 TCLK cycles for STS-3c or every 810 TCLK cycles for STS-1. It is updated
on the rising edge of TCLK.
Pin #: 53
Input provides the ability to insert GFC values downstream of the transmit FIFO. The four
TCLK periods following TCP output pulse should contain the four GFC bits to be inserted.
The GFC enable bits in a configuration register enable the insertion of each bit. By default,
the GFC values contain the header information of the default idle/unassigned cell header
register. The inserted GFC bits are input into the next immediate cell to be transmitted. TGFC
bits are sampled on the rising edge of TCLK.
Pin #: 52
Differential input contain a jitter-free 19.44 MHz or a 6.48 MHz reference clock when clock
synthesis is enabled (TBYP = 0). When TBYP is enabled, TRCLK+/- is nominally a 155.52
MHz or 51.84 MHz 50% duty cycle clock and provides the timing for the internal transmit
functions. It may be left unconnected if loop timing is enabled.
Pin #: TRCLK+/10, TRCLK-/9
The tristate enable signal tristates RSOC, RDAT[7:0], and RXPRTY signals. When asserted,
RSOC, RDAT[7:0], and RXPRTY are driven only when RRDENB is asserted. When TSEN is
low, the signals RSOC, RDAT[7:0], and RXPRTY, are always asserted in single-phy UTOPIA
level-1 mode. TSEN has an integral pull-down resistor.
Pin #: 66
The transmit start of cell indication from ATM layer. This should be asserted during the first
byte of each cell and is sampled on the rising edge of TFCLK. An interrupt is generated while
TSOC is asserted at any byte other than the first byte of the transmit 53 byte cell.
Pin #: 96
Active low transmit enable signal used to initiate writes to the transmit FIFO from the ATM
device. When asserted low, the byte on TDAT[7:0] is written to the transmit FIFO. A complete
53 byte cell must be written to the FIFO before the cell is inserted into the SPE of the transmit
frame. Idle/unassigned cells are inserted until a complete cell is available for transmission.
Pin #: 85
Indicates the ID of the device which should respond to the transmit bus signals in
transmit bus signals in UTOPIA level-2 multi-phy mode (when MPHYEN is asserted). It
indicates the device which should accept the transmit cell from ATM device. The device ID
may be programmed in a transmit ID register. The device ID register contain a default
address of 0. TXADDR[1:0] is sampled on the rising edge of TFCLK. TXADDR[1:0] inputs
have integral pull-up resistors. TXADDR[1:0] inputs are ignored when MPHYEN is not
asserted.
Pin #: TXADDR0/48, TXADDR1/47
Transmit differential line negative output clock is a buffered version of the input differential
clock. These outputs could be programmed to be pure PECL. Default is a rail-to-rail swing, If
these outputs are not programmed to be PECL, then the outputs are squelched in the STS-3c
mode.
Pin #: TSC+/13, TXC-/14
NRZ encoded transmit differential data outputs which contain STS-3c or STS-1 data, and
updated on the falling edge of TXC+/-. These outputs could be programmed to be pure PECL.
Default is a rail-to-rail swing.
Pin #: TXD+/15, TXD-/16
Indicates the parity of the TDAT[7:0] bus. Odd or even parity may be selected. TXPRTY is
sampled on the rising edge of TFCLK and considered valid only when TWRENB is asserted.
TXPRTY has an integral pull-down resistor. A maskable parity error is generated if an error is
detected, but the cells with parity errors are not filtered.
Pin #: 95
Power pin for TXC+/- and TXD+/- outputs. Should be physically isolated from the other power
analog pins and connected to a well coupled 5v dc source.
Pin #: 12
TGFC
Transmit Generic
Flow Control
I
TRCLK+
TRCLK-
Transmit
Reference Clock
I
TSEN
Transmit Enable
I
TSOC
Transmit Start of
Cell
I
TWRENB
Transmit Write
Enable
I
TXADDR[0]
TXADDR[1]
Transmit Address
I
TXC+
TXC-
Transmit Clock
O
TXD+
TXD-
Transmit Data
O
TXPRTY
Transmit Parity
I
TXVcc
Power
P
PIN DESCRIPTIONS (CONTINUED)
相關(guān)PDF資料
PDF描述
IDT77155 PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
IDT77155L155PX PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
IDT77301 UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
IDT77301L12PF UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
IDT77301L12PFI UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
相關(guān)代理商/技術(shù)參數(shù)
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IDT77V011L155DA 功能描述:INTERFACE DPI-UTOPIA 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
IDT77V011L155DA8 功能描述:INTERFACE DPI-UTOPIA 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
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