參數(shù)資料
型號(hào): IDT77155L155
廠商: Integrated Device Technology, Inc.
英文描述: PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
中文描述: 物理層(增距鏡TC - PMD)的用戶網(wǎng)絡(luò)接口的155Mbps的ATM網(wǎng)絡(luò)中的應(yīng)用
文件頁(yè)數(shù): 22/50頁(yè)
文件大?。?/td> 307K
代理商: IDT77155L155
8.03
22
IDT77155
155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION
Commercial Temperature Range
RECEIVE SECTION OVERHEAD CONTROL REGISTER
ADDRESS 0X10
DEFAULT = 8’B00000000
Bit
Bit 7
Bit 6
Bit 5
Type
R/W
W
Symbol
scrDis
frcOOF
Function
Reserved
Disable receive frame scrambler if set to logic one.
When set to logic one, the receive section overhead logic is forced out of
frame at the next frame boundary.
Reserved
Interrupt enable for rx section BIP (B1) error. When asserted, an interrupt
is generated if section BIP (B1) error is detected.
Receive loss of signal interrupt enable. When asserted, an interrupt is
generated if LOS alarm changes state.
Receive loss of frame interrupt enable. When set to logic one, an interrupt
is generated if LOF alarm changes state.
Receive out of frame interrupt enable. When set to logic one, an interrupt
is generated if OOF alarm changes state.
Bit 4
Bit 3
R/W
B1ErrIEn
Bit 2
R/W
LOSIEn
Bit 1
R/W
LOFIEn
Bit 0
R/W
OOFIEn
RECEIVE SECTION OVERHEAD STATUS REGISTER DEFAULT = 8’BXXXXXXXX
ADDRESS 0X11
Bit
Bit 7
Type
R
Symbol
C1Int
Function
Interrupt bit set if received C1 bytes received do not correspond to 1, 2, 3
respectively. This bit is cleared when this register is read.
Interrupt is asserted if section BIP (B1) errors received. This bit is cleared
when this register is read.
Loss of signal interrupt is asserted if LOS changes state. This bit is
cleared when this register is read.
Loss of frame interrupt is asserted if LOF changes state. This bit is
cleared when this register is read.
Out of frame interrupt is asserted if OOF changes state. This bit is
cleared when this register is read.
Loss of signal status indication. Asserted high.
Loss of frame status indication. Asserted high.
Out of frame status indication. Asserted high.
Bit 6
R
B1ErrInt
Bit 5
R
LOSInt
Bit 4
R
LOFInt
Bit 3
R
OOFInt
Bit 2
Bit 1
Bit 0
R
R
R
LOS
LOF
OOF
RECEIVE SECTION BIP ERROR COUNTER
DEFAULT = 16’HXXXX
ADDRESS 0X12
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Symbol
B1ErrCnt[7]
B1ErrCnt[6]
B1ErrCnt[5]
B1ErrCnt[4]
B1ErrCnt[3]
B1ErrCnt[2]
B1ErrCnt[1]
B1ErrCnt[0]
Function
B1 error counter bit
B1 error counter bit
B1 error counter bit
B1 error counter bit
B1 error counter bit
B1 error counter bit
B1 error counter bit
B1 error counter bit
相關(guān)PDF資料
PDF描述
IDT77155 PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
IDT77155L155PX PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
IDT77301 UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
IDT77301L12PF UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
IDT77301L12PFI UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
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