參數(shù)資料
型號： IDT82P2821BH
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 121/151頁
文件大小： 0K
描述： IC LIU T1/J1/E1 21+1CH 640-PBGA
標準包裝： 5
功能： 線路接口單元（LIU）
接口： E1，J1，T1
電路數(shù)： 1
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 640-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 640-PBGA-EP（31x31）
包裝： 托盤
包括： 缺陷和警報檢測，驅(qū)動器過流檢測和保護，LLOS 檢測，PRBSARB / IB 檢測和生成
其它名稱： 82P2821BH
IDT82P2821
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Miscellaneous
71
February 6, 2009
4.3
POWER UP
No power up sequencing for the VDD inputs (1.8 V and 3.3 V) has to
be provided for the IDT82P2821. A Power-on reset will be initiated
during power up. Refer to Section 4.1 Reset.
4.4
HITLESS PROTECTION SWITCHING (HPS) SUM-
MARY
In today’s telecommunication systems, ensuring no traffic loss is
becoming increasingly important. To combat these problems, redun-
dancy protection must be built into the systems carrying this traffic.
There are many types of redundancy protection schemes, including 1+1
and 1:1 hardware protection without the use of external relays. Refer to
Figure-46, Figure-47 and Figure-48 for different protection schemes.
The IDT82P2821 provides an enhanced architecture to support both
protection schemes.
IDT82P2821 highlights for HPS support:
Independent programmable receive and transmit high impedance
for Tip and Ring inputs and outputs to support 1+1 and 1:1 redun-
dancy
Fully integrated receive termination, required to support 1:1 redun-
dancy
Enhanced internal architecture to guarantee High Impedance for
Tip and Ring Inputs and Outputs during Power Off or Power Fail-
ure
Asynchronous hardware control (OE, RIM) for fast global high
impedance of receiver and transmitter (hot switching between
working and backup board)
Figure-46 1+1 HPS Scheme, Differential Interface (Shared Common Transformer)
1:2
Tx
LIU on primary line card
LIU on backup line card
backplane
interface card
1:1
Tx
Rx
120
OE
RIM
OE
RIM
Hot switch control
VDDTn
VDDTn
VDDRn
VDDRn
VDDTn
VDDTn
VDDRn
VDDRn
Rx:
Partially Internal Impedance Matching mode. A fixed external 120
resistor is placed on the backplane and provides a common termination for
T1/J1/E1 applications. The R_TERM[2:0] bits (b2~0, RCF0,...) setting is as follows: ‘000’ for T1 100
twisted pair cable, ‘001’ for J1 110 twisted
pair cable, ‘010’ for E1 120
twisted pair cable and ‘011’ for E1 75 coaxial cable.
Tx:
Internal Impedance Matching mode. The
T_TERM[2:0] bits (b2~0, TCF0,...) setting is as follows: ‘000’ for T1 100 twisted pair cable, ‘001’
for J1 110
twisted pair cable, ‘010’ for E1 120 twisted pair cable and ‘011’ for E1 75 coaxial cable.
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