參數(shù)資料
型號: IDT82P2821BH
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 139/151頁
文件大?。?/td> 0K
描述: IC LIU T1/J1/E1 21+1CH 640-PBGA
標準包裝: 5
功能: 線路接口單元(LIU)
接口: E1,J1,T1
電路數(shù): 1
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 640-BGA 裸露焊盤
供應商設備封裝: 640-PBGA-EP(31x31)
包裝: 托盤
包括: 缺陷和警報檢測,驅動器過流檢測和保護,LLOS 檢測,PRBSARB / IB 檢測和生成
其它名稱: 82P2821BH
IDT82P2821
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Programming Information
88
February 6, 2009
RJA - Receive Jitter Attenuation Configuration Register
Address: 003H, 043H, 083H, 0C3H, 103H, 143H, 183H, 1C3H, (CH1~CH8)
203H, 243H, 283H, 2C3H, 303H, 343H, 383H, 3C3H, (CH9~CH16)
403H, 443H, 483H, 4C3H, 503H, (CH17~CH21)
7C3H (CH0)
Type: Read / Write
Default Value: 00H
Bit
Name
Description
7 - 5
-
Reserved.
4
RJA_LIMT
This bit determines whether the JA-Limit function is enabled in the RJA.
0: Disable. (default)
1: Enable. The speed of the RJA outgoing data will be adjusted automatically if the FIFO in the RJA is 2-bit close to its full or
emptiness.
3
RJA_EN
This bit controls whether the RJA is enabled to use.
0: Disable. (default)
1: Enable.
2 - 1
RJA_DP[1:0]
These bits select the depth of the RJA FIFO.
00: 128-bit. (default)
01: 64-bit.
1X: 32-bit.
0
RJA_BW
This bit selects the Corner Frequency for the RJA.
0: 5 Hz (in T1/J1 mode) / 6.77 Hz (in E1 mode). (default)
1: 1.26 Hz (in T1/J1 mode) / 0.87 Hz (in E1 mode).
7
654321
0
-
RJA_LIMT
RJA_EN
RJA_DP1
RJA_DP0
RJA_BW
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