參數資料
型號: IDT82P2821BH
廠商: IDT, Integrated Device Technology Inc
文件頁數: 69/151頁
文件大?。?/td> 0K
描述: IC LIU T1/J1/E1 21+1CH 640-PBGA
標準包裝: 5
功能: 線路接口單元(LIU)
接口: E1,J1,T1
電路數: 1
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 640-BGA 裸露焊盤
供應商設備封裝: 640-PBGA-EP(31x31)
包裝: 托盤
包括: 缺陷和警報檢測,驅動器過流檢測和保護,LLOS 檢測,PRBSARB / IB 檢測和生成
其它名稱: 82P2821BH
IDT82P2821
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Pin Description
24
February 6, 2009
OE
Input
AJ10
OE: Output Enable
OE enables or disables all Line Drivers globally.
A high level on this pin enables all Line Drivers while a low level on this pin places all Line
Drivers in High-Z state and independent from related register settings.
Note that the functionality of the internal circuit is not affected by OE.
If this pin is not used, it should be tied to VDDIO.
This pin can be used to control the transmit impedance state for Hitless protection applica-
TEHWE
Input
(Pull-Up)
AF11
TEHWE: Hardware T1/J1 or E1 Mode Selection Enable
When this pin is open, the T1/J1 or E1 operation mode is selected by TEHW globally.
When this pin is low, the T1/J1 or E1 operation mode is selected by the T1E1 bit (b0,
CHCF,...) on a per-channel basis.
TEHW
Input
(Pull-Up)
AF12
TEHW: Hardware T1/J1 or E1 Mode Selection
When TEHWE is open, this pin selects the T1/J1 or E1 operation mode globally:
Low - E1 mode;
Open - T1/J1 mode.
When TEHWE is low, the input on this pin is ignored.
GPIO[0]
GPIO[1]
Output / Input
AF9
AF10
GPIO: General Purpose I/O [1:0]
These two pins can be defined as input pins or output pins by the DIR[1:0] bits (b1~0, GPIO)
respectively.
When the pins are input, their polarities are indicated by the LEVEL[1:0] bits (b3~2, GPIO)
respectively.
When the pins are output, their polarities are controlled by the LEVEL[1:0] bits (b3~2, GPIO)
respectively.
RST
Input
AG10
RST: Reset (Active Low)
A low pulse on this pin resets the device. This hardware reset process completes in 2 s max-
imum. Refer to Section 4.1 Reset for an overview on reset options.
MCU Interface
INT
Output
AK16
INT: Interrupt Request
This pin indicates interrupt requests for all unmasked interrupt sources.
The output characteristics (open drain or push-pull internally) and the active level are deter-
mined by the INT_PIN[1:0] bits (b3~2, GCF).
CS
Input
AJ17
CS: Chip Select (Active Low)
This pin must be asserted low to enable the microprocessor interface.
A transition from high to low must occur on this pin for each Read/Write operation and CS
should remain low until the operation is over.
P/S
Input
AG16
P/S: Parallel or Serial Microprocessor Interface Select
P/S selects Serial or Parallel microprocessor interface for the device:
GNDD - Serial microprocessor interface.
VDDIO - Parallel microprocessor interface.
Serial microprocessor interface consists of the CS, SCLK, SDI, SDO pins.
Parallel microprocessor interface consists of the CS, INT/MOT, IM, DS/RD, ALE/AS, R/W/WR,
ACK/RDY, D[7:0], A[10:0] pins.
INT/MOT
Input
(Pull-Up)
AF14
INT/MOT: Intel or Motorola Microprocessor Interface Select
In Parallel microprocessor interface, INT/MOT selects Intel or Motorola microprocessor inter-
face for the device:
GNDD - Parallel Motorola microprocessor interface.
Open - Parallel Intel microprocessor interface.
In Serial microprocessor interface, this pin should be left open.
Name
I / O
Pin No.
Description
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