參數(shù)資料
型號： IDT82P2916BFG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 14/138頁
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 16CH SH 484BGA
標(biāo)準(zhǔn)包裝： 84
功能： 線路接口單元（LIU）
接口： E1，J1，T1
電路數(shù)： 16
電源電壓： 1.8V, 3.3V
功率（瓦特）： 3.10W
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 484-LFBGA
供應(yīng)商設(shè)備封裝： 484-CABGA（19x19）
包裝： 托盤
包括： AIS 警報檢測器和發(fā)生器，回送功能，PRBS 發(fā)生器 / 檢測器，遠(yuǎn)程檢測器和發(fā)生器
IDT82P2916
16-CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
JTAG
110
April 24, 2010
6JTAG
The IDT82P2916 supports the digital Boundary Scan Specification
as described in the IEEE 1149.1 standards.
The boundary scan architecture consists of data and instruction
registers plus a Test Access Port (TAP) controller. The control of the TAP
is achieved through signals applied to the Test Mode Select (TMS) and
Test Clock (TCK) input pins. Data is shifted into the registers via the Test
Data Input (TDI) pin, and shifted out of the registers via the Test Data
Output (TDO) pin. Both TDI and TDO are clocked at a rate determined
by TCK.
The JTAG boundary scan registers include BSR (Boundary Scan
Register), DIR (Device Identification Register), BR (Bypass Register)
and IR (Instruction Register). These will be described in the following
pages. Refer to Figure-45 for architecture.
Figure-45 JTAG Architecture
6.1
JTAG INSTRUCTION REGISTER (IR)
The IR with instruction decode block is used to select the test to be
executed or the data register to be accessed or both.
The instructions include: EXTEST, SAMPLE/PRELOAD, IDCODE,
BYPASS, CLAMP and HIGHZ.
6.2
JTAG DATA REGISTER
6.2.1
DEVICE IDENTIFICATION REGISTER (IDR)
The IDR can be set to define the Version, the Part Number, the
Manufacturer Identity and a fixed bit.
6.2.2
BYPASS REGISTER (BYP)
The BYP consists of a single bit. It can provide a serial path between
the TDI input and the TDO output. Bypassing the BYR will reduce test
access times.
6.2.3
BOUNDARY SCAN REGISTER (BSR)
The bidirectional ports interface to 2 boundary scan cells:
- In cell: The input cell is observable only.
- Out cell: The output cell is controllable and observable.
6.3
TEST ACCESS PORT (TAP) CONTROLLER
The TAP controller is a 16-state synchronous state machine. The
states include: Test Logic Reset, Run-Test/Idle, Select-DR-Scan,
Capture-DR, Shift-DR, Exit1-DR, Pause-DR, Exit2-DR, Update-DR,
Select-IR-Scan, Capture-IR, Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and
Update-IR.
Figure-46 shows the state diagram. Note that the figure contains two
main branches to access either the data or instruction registers. The
value shown next to each state transition in this figure states the value
present at TMS at each rising edge of TCK.
BSR (Boundary Scan Register)
DIR (Device Identification Register)
BR (Bypass Register)
IR (Instruction Register)
MUX
TDO
TDI
TCK
TMS
TRST
Control
MUX
Select
Output Enable
TAP
(Test Access
Port) Controller
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IDT82P2916BFG8 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA
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