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參數(shù)資料
| 型號： | IDT82P2916BFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 35/138頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 16CH SH 484BGA |
| 標準包裝： | 84 |
| 功能： | 線路接口單元（LIU） |
| 接口： | E1，J1，T1 |
| 電路數(shù)： | 16 |
| 電源電壓： | 1.8V, 3.3V |
| 功率（瓦特）： | 3.10W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 484-LFBGA |
| 供應商設備封裝： | 484-CABGA（19x19） |
| 包裝： | 托盤 |
| 包括： | AIS 警報檢測器和發(fā)生器，回送功能，PRBS 發(fā)生器 / 檢測器，遠程檢測器和發(fā)生器 |
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IDT82P2916
16-CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Pin Description
13
April 24, 2010
2
PIN DESCRIPTION
Name
I / O
Pin No. 1
Description
Line Interface
RTIPn
RRINGn
(n=0~15)
Input
L3, M3, N3, P3, R3, R20, P20, N20,
K20, J20, H20, G20, G3, H3, J3, K3
L4, M4, N4, P4, R4, R19, P19, N19,
K19, J19, H19, G19, G4, H4, J4, K4
RTIPn / RRINGn: Receive Bipolar Tip/Ring for Channel 0 ~ 15
The receive line interface supports both Receive Differential mode and Receive Single Ended
mode.
In Receive Differential mode, the received signal is coupled into RTIPn and RRINGn via a 1:1
transformer or without a transformer (transformer-less).
In Receive Single Ended mode, RRINGn should be left open. The received signal is input on
RTIPn via a 2:1 (step down) transformer or without a transformer (transformer-less).
These pins will become High-Z globally or channel specific in the following conditions:
Global High-Z:
- Connecting the RIM pin to low;
- Loss of MCLK
- During and after power-on reset, hardware reset or global software reset;
Per-channel High-Z
- Receiver power down by writing ‘1’ to the R_OFF bit (b5, RCF0,...)
TTIPn
TRINGn
(n=0~15)
Output
M1, P1, T1, V1, Y1, V22, T22, P22,
M22, K22, H22, F22, D1, F1, H1, K1
L1, N1, R1, U1, W1, U22, R22, N22,
L22, J22, G22, E22, C1, E1, G1, J1
TTIPn / TRINGn: Transmit Bipolar Tip /Ring for Channel 0 ~ 15
The transmit line interface supports both Transmit Differential mode and Transmit Single
Ended mode.
In Transmit Differential mode, TTIPn outputs a positive differential pulse while TRINGn out-
puts a negative differential pulse. The pulses are coupled to the line side via a 1:2 (step up)
transformer or without a transformer (transformer-less).
In Transmit Single Ended mode, TRINGn should be left open (it is shorted to ground inter-
nally). The signal presented at TTIPn is output to the line side via a 1:2 (step up) transformer.
These pins will become High-Z globally or channel specific in the following conditions:
Global High-Z:
- Connecting the OE pin to low;
- Loss of MCLK;
- During and after power-on reset, hardware reset or global software reset;
Per-channel High-Z
- Loss of TCLKn in Transmit Single Rail NRZ Format mode or Transmit Dual Rail NRZ
Format mode, except that the channel is in Remote Loopback or transmit internal pat-
tern with XCLK 3;
- Transmitter power down by writing ‘1’ to the
T_OFF bit (b5, TCF0,...);
- Per-channel software reset;
- The THZ_OC bit (b4, TCF0,...) is set to ‘1’ and the transmit driver over-current is
detected.
Refer to Section 3.3.8 Output High-Z on TTIP and TRING for details.
Note:
1. The pin number of the pins with the footnote ‘n’ is listed in order of channel (CH0 ~ CH15).
2. The content in the brackets indicates the position and the register name of the preceding bit. After the register name, if the punctuation ‘,...’ is followed, this bit is in a per-channel register.
The addresses and details are included in Chapter 5 Programming Information.
3. XCLK is derived from MCLK. It is 1.544 MHz in T1/J1 mode or 2.048 MHz in E1 mode.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82P2916BFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA |
| IDT82P5088 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Universal Octal T1/E1/J1 LIU with Integrated Clock Adapter |
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| IDT82P5088BBG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 OCTAL 256PBGA |
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