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參數(shù)資料
| 型號(hào)： | IDT82P2916BFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 67/138頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 16CH SH 484BGA |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 功能： | 線路接口單元（LIU） |
| 接口： | E1，J1，T1 |
| 電路數(shù)： | 16 |
| 電源電壓： | 1.8V, 3.3V |
| 功率（瓦特）： | 3.10W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 484-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 484-CABGA（19x19） |
| 包裝： | 托盤 |
| 包括： | AIS 警報(bào)檢測(cè)器和發(fā)生器，回送功能，PRBS 發(fā)生器 / 檢測(cè)器，遠(yuǎn)程檢測(cè)器和發(fā)生器 |
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IDT82P2916
16-CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Functional Description
34
April 24, 2010
3.3.7
TRANSMITTER POWER DOWN
Set the T_OFF bit (b5, TCF0,...) to ‘1’ will power down the corre-
sponding transmitter.
In this way, the corresponding transmit circuit is turned off. The pins
on the transmit line interface (including TTIPn and TRINGn) will be in
High-Z state. The input on the transmit system interface (including TDn,
TDPn, TDNn and TCLK) is ignored. The output on the transmit system
interface (i.e. TMFn) will be in High-Z state.
After clearing the T_OFF bit (b5, TCF0,...), it will take 1 ms for the
transmitter to achieve steady state, i.e., return to the previous configura-
tion and performance.
3.3.8
OUTPUT HIGH-Z ON TTIP AND TRING
TTIPn and TRINGn can be set to High-Z state globally or on a per-
channel basis.
The following three conditions will set TTIPn and TRINGn to High-Z
state globally:
Connecting the OE pin to low;
Loss of MCLK (i.e., no transition on MCLK for more than 1 ms);
Power on reset, hardware reset by pulling RST to low for more
than 2 s or global software reset by writing the RST register.
The following six conditions will set TTIPn and TRINGn to High-Z
state on a per-channel basis:
Writing ‘0’ to the OE bit (b6, TCF0,...);
Loss of TCLKn in Transmit Single Rail NRZ Format mode or
Transmit Dual Rail NRZ Format mode (i.e., no transition on TCLKn
for more than 64 XCLK1 cycles) except that the channel is in
Remote Loopback or transmit internal pattern with XCLK;
Transmitter power down;
Per-channel software reset by writing ‘1’ to the CHRST bit (b1,
Setting the THZ_OC bit (b4, TCF0,...) to ‘1’ when transmit driver
over-current is detected.
1. XCLK is derived from MCLK. It is 1.544 MHz in T1/J1 mode or 2.048 MHz
in E1 mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82P2916BFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA |
| IDT82P5088 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Universal Octal T1/E1/J1 LIU with Integrated Clock Adapter |
| IDT82P5088BBBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Universal Octal T1/E1/J1 LIU with Integrated Clock Adapter |
| IDT82P5088BBG | 功能描述:IC LIU T1/E1/J1 OCTAL 256PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| IDT82P5088BBG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 OCTAL 256PBGA |
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