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參數(shù)資料
| 型號： | IDT82V2048EBBG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 15/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LINE INTERFACE UNIT 208-PBGA |
| 標準包裝： | 10 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-BGA |
| 供應商設(shè)備封裝： | 208-PBGA（17x17） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 1259 (CN2011-ZH PDF) |
| 其它名稱： | 800-1704 82V2048EBBG |
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22
INDUSTRIAL
TEMPERATURE RANGES
OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
3.3.2
LINE MONITOR
In both T1/J1 and E1 short haul applications, the non-intrusive monitor-
ingonchannelslocatedinotherchipscanbeperformedbytappingthemon-
itored channel through a high impedance bridging circuit. Refer to Figure-
After a high resistance bridging circuit, the signal arriving at the RTIPn/
RRINGn is dramatically attenuated. To compensate this attenuation, the
Monitor Gain can be used to boost the signal by 22 dB, 26 dB and 32 dB,
selected by MG[1:0] bits (RCF2, 09H...). For normal operation, the Monitor
Gain should be set to 0 dB.
Figure-10 Monitoring Receive Line in Another Chip
Figure-11 Monitor Transmit Line in Another Chip
3.3.3
ADAPTIVE EQUALIZER
The Adaptive Equalizer can be enabled to increase the receive sensi-
tivity and to allow programming of the LOS level up to -24 dB. See section
3.5 LOS AND AIS DETECTION. It can be enabled or disabled by setting
EQ_ON bit to ‘1’ or ‘0’ (RCF1, 08H...).
3.3.4
RECEIVE SENSITIVITY
The Receive Sensitivity for both E1 and T1/J1 is -10 dB. With the Adap-
tive Equalizer enabled, the receive sensitivity will be -20 dB.
3.3.5
DATA SLICER
The Data Slicer is used to generate a standard amplitude mark or a
space according to the amplitude of the input signals. The threshold can
be 40%, 50%, 60% or 70%, as selected by the SLICE[1:0] bits (RCF2,
09H...). The output of the Data Slicer is forwarded to the CDR (Clock & Data
Recovery) unit or to the RDPn/RDNn pins directly if the CDR is disabled.
3.3.6
CDR (Clock & Data Recovery)
The CDR is used to recover the clock from the received signals. The
recovered clock tracks the jitter in the data output from the Data Slicer and
keeps the phase relationship between data and clock during the absence
of the incoming pulse. The CDR can also be by-passed in the Dual Rail
mode. When CDR is by-passed, the data from the Data Slicer is output to
the RDPn/RDNn pins directly.
3.3.7
DECODER
In T1/J1 applications, the R_MD[1:0] bits (RCF0, 07H...) is used to
selecttheAMIdecoderorB8ZSdecoder.InE1applications,theR_MD[1:0]
bits (RCF0, 07H...) are used to select the AMI decoder or HDB3 decoder.
3.3.8
RECEIVE PATH SYSTEM INTERFACE
The receive path system interface consists of RCLKn pin, RDn/RDPn
pin and RDNn pin. In E1 mode, the RCLKn outputs a recovered 2.048 MHz
clock.InT1/J1mode,theRCLKnoutputsarecovered1.544MHzclock.The
received data is updated on the RDn/RDPn and RDNn pins on the active
edge of RCLKn. The active edge of RCLKn can be selected by the
RCLK_SEL bit (RCF0, 07H...). And the active level of the data on RDn/
RDPn and RDNn can also be selected by the RD_INV bit (RCF0, 07H...).
Single Rail or Dual Rail, as selected by R_MD bit [1] (RCF0, 07H...). In
Single Rail mode, only RDn pin is used to output data and the RDNn/CVn
pin is used to report the received errors. In Dual Rail Mode, both RDPn pin
and RDNn pin are used for outputting data.
In the receive Dual Rail mode, the CDR unit can be by-passed by setting
R_MD[1:0] to ‘11’ (binary). In this situation, the output data from the Data
Slicer will be output to the RDPn/RDNn pins directly, and the RCLKn out-
puts the exclusive OR (XOR) of the RDPn and RDNn.
3.3.9
RECEIVE PATH POWER DOWN
The receive path can be powered down individually by setting R_OFF
bit (RCF0, 07H...) to ‘1’. In this case, the RCLKn, RDn/RDPn, RDPn and
LOSn will be logic low.
RTIP
RRING
RTIP
RRING
normal receive mode
monitor mode
DSX cross connect
point
R
monitor gain
=22/26/32dB
monitor
gain=0dB
TTIP
TRING
RTIP
RRING
normal transmit mode
monitor mode
DSX cross connect
point
R
monitor gain
=22/26/32dB
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