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參數(shù)資料
| 型號： | IDT82V2048EBBG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 5/76頁 |
| 文件大小： | 0K |
| 描述： | IC LINE INTERFACE UNIT 208-PBGA |
| 標(biāo)準(zhǔn)包裝： | 10 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-BGA |
| 供應(yīng)商設(shè)備封裝： | 208-PBGA（17x17） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 1259 (CN2011-ZH PDF) |
| 其它名稱： | 800-1704 82V2048EBBG |
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13
INDUSTRIAL
TEMPERATURE RANGES
OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
DS/RD
Input
47
N3
DS: Data Strobe
In parallel Motorola microcontroller interface mode, signal on this pin is the data strobe of the parallel
interface. During a write operation (R/W =0), data on D[7:0] is sampled into the device. During a read
operation (R/W =1), data is output to D[7:0] from the device.
RD: Read Operation
In parallel Intel microcontroller interface mode, this pin is asserted low by the microcontroller to initiate
a read cycle. Data is output to D[7:0] from the device during a read operation.
SDI/R/W/WR
Input
48
P1
SDI: Serial Data Input
In serial microcontroller interface mode, data is input on this pin. Input data is sampled on the rising
edges of SCLK.
R/W: Read/Write Select
In parallel Motorola microcontroller interface mode, this pin is low for write operation and high for read
operation.
WR: Write Operation
In parallel Intel microcontroller interface mode, this pin is asserted low by the microcontroller to initiate
a write cycle. Data on D[7:0] is sampled into the device during a write operation.
SDO
Output
49
P2
SDO: Serial Data Output
In serial microcontroller interface mode, signal on this pin is the output data of the serial interface. Con-
figuration and status data on pin SDO is clocked out of the device on the active edge of SCLK.
INT
Output
50
R1
INT: Interrupt Request
This pin outputs the general interrupt request for all interrupt sources. If INTM_GLB bit (GCF0, 40H)
is set to ‘1’, all interrupt sources will be masked. And these interrupt sources also can be masked indi-
vidually via registers (INTM0, 11H) and (INTM1, 12H). Interrupt status is reported via byte INT_CH
(INTCH, 80H), registers (INTS0, 16H) and (INTS1, 17H).
Output characteristics of this pin can be defined to be push-pull (active high or low) or be open-drain
(active low) by bits INT_PIN[1:0] (GCF0, 40H).
D7
D6
D5
D4
D3
D2
D1
D0
I / O
24
25
26
27
28
29
30
31
H3
H2
J1
J2
J3
J4
K3
K2
Dn: Data Bus 7~0
These pins function as a bi-directional data bus of the microcontroller interface.
A7
A6
A5
A4
A3
A2
A1
A0
Input
37
38
39
40
41
42
43
44
L1
L2
L3
L4
M4
M3
M2
M1
An: Address Bus 7~0
These pins function as an address bus of the microcontroller interface.
RST
Input
51
P3
RST: Hardware Reset
The chip is reset if a low signal is applied on this pin for more than 100ns. All the drivers output are in
high impedance state, all the internal flip-flops are reset and all the registers are initialized to their
default values.
THZ
Input
10
E4
THZ: Transmit Driver Enable
This pin enables or disables all transmitter drivers on a global basis. A low level on this pin enables the
drivers while a high level turns all drivers into high impedance state. Note that functionality of internal
circuits is not affected by signal on this pin.
REF
Input
59
T1
REF: Reference Resistor
An external resistor (3 K
, 1%) is used to connect this pin to ground to provide a standard reference
current for internal circuit.
Table-1 Pin Description (Continued)
Name
Type
Pin No.
Description
PQFP208
PBGA208
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