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| 型號(hào)： | IDT82V2108BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 284/292頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FRAMER T1/J1/E1 8CH 144-BGA |
| 標(biāo)準(zhǔn)包裝： | 10 |
| 控制器類型： | T1/E1/J1 調(diào)幀器 |
| 接口： | 并聯(lián) |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 電流 - 電源： | 160mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-BGA |
| 供應(yīng)商設(shè)備封裝： | 144-PBGA（13x13） |
| 包裝： | 托盤 |
| 其它名稱： | 82V2108BB |
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IDT82V2108
T1 / E1 / J1 OCTAL FRAMER
Functional Description
81
March 5, 2009
3.15.2
T1/J1 MODE
In T1/J1 mode, the data to be transmitted can be either the Super
Frame (SF) or the Extended Super Frame (ESF) format. The selection is
made by the ESF (b4, T1/J1-044H).
The SF/ESF is generated on the base of the UF (b6, T1/J1-046H)
and the FDIS (b3, T1/J1-006H) are logic 0, that is, the F-bit can be
replaced with the Frame Alignment Pattern, DL and CRC-6 (the DL and
CRC-6 bits only exist in the ESF format). Thus, the FAS can be replaced
in its position when the FBITBYP (b2, T1/J1-006H) is logic 0. In the SF
format, the Frame Alignment Pattern is ‘10001101110X’ and replaces
the F-bit of each frame input from the TSDn pin (refer to Table 3). In the
ESF format, the Frame Alignment Pattern is ‘001011’ and replaces the
F-bit in every 4th frame starting with Frame 4. The CRC-6 will replace
the F-bit in every 4th frame starting with Frame 2 if the CRCBYP (b1, T1/
J1-006H) is logic 0. The CRC-6 algorithm is chosen between the T1
standard and the J1 standard by the J1_CRC (b6, T1/J1-044H). The DL
bits will replace the F-bit in every other frame starting with Frame 1 when
the FDLBYP (b0, T1/J1-006H) is logic 0 (refer to Table 4).
Before the data coming into the Frame Generator, if the SIGC[1:0]
(b7~6, T1/J1-TPLC-indirect registers - 31~48H) select the signaling bit
input from the TSDn pin to be replaced with the signaling input from the
TSSIGn pin, the signaling bit of all channels can be replaced with the
signaling of the 1st frame when the SIGAEN (b5, T1/J1-006H) is set.
This configuration is to avoid the signaling change in the middle of a SF/
ESF.
The data input from the TSDn pin will be replaced by the code set
in the IDLE[7:0] (b7~0, T1/J1-TPLC-indirect registers - 19~30H) when
the MTRK (b7, T1/J1-044H) is set. When the MTRK (b7, T1/J1-044H) is
set, the signaling bits of all channels may also be replaced by the signal-
ing input from the TSSIGn pin or the data set in the A, B, C, D (b3~0, T1/
J1-TPLC-indirect registers - 31~48H) according to the setting in the
SIGC[1:0] (b7~6, T1/J1-TPLC-indirect registers - 31~48H). The MTRK
(b7, T1/J1-044H) takes effect only when the PCCE (b0, T1/J1-030H) in
the TPLC is logic 1.
Configured by the TXMFP (b1, T1/J1-00AH), a mimic pattern can
be inserted in the 1st bit of each channel. The content of the mimic pat-
tern is the same as the F-bit. The mimic pattern insertion is for diagnos-
tic purposes.
The Yellow alarm signal can be inserted in the data stream to be
transmitted when the XYEL (b2, T1/J1-045H) is enabled. The alarm sig-
nal pattern is chosen between the T1 and J1 mode by the J1_YEL (b5,
T1/J1-044H). The pattern is:
- In T1 SF format: Transmit the logic 0 on the 2nd bit of each chan-
nel.
- In J1 SF format: Transmit the logic 1 on the 12th F-bit.
- In T1 ESF format: Transmit the ‘FF00’ on each DL of F-bit.
- In J1 ESF format: Transmit the ‘FFFF’ on each DL of F-bit.
The Yellow alarm signal can also be inserted automatically by set-
ting the AUTOYELLOW (b3, T1/J1-000H) when Red alarm is declared in
the received data stream.
In the ESF format, if the Yellow alarm signal is stopped by setting
the XYEL (b2, T1/J1-045H) to be logic 0, a Yellow alarm disabled pattern
will be transmitted automatically. In T1 mode, the pattern is ‘FFFF’. In J1
mode, the pattern is ‘FF7E’. The disable pattern should be repeated 16
times before the BOC (refer to Chapter 3.17 Bit-Oriented Message
Transmitter (TBOM) - T1/J1 Only) or the HDLC bits (refer to
Chapter 3.16 HDLC Transmitter (THDLC)) are inserted in the DL bit.
The Yellow alarm takes the highest priority in these three kinds of inser-
tion.
If there are no Yellow alarm signal, no BOC, no HDLC bits or no
TPLC insertion in the DL of the F-bit, the DL position will be forced to
transmit ‘FFFF’ in T1 mode or ‘7E7E’ in J1 mode continuously.
A FIFO is employed in the Frame Generator to store the data
stream to be transmitted. The FIFO can be initiated by setting the
FRESH (b7, T1/J1-006H).
Table 38: Interrupt Summary in E1 Mode
No.
Interrupt Sources
Indication Bits
Interrupt Mask Bits
1 The end of the first frame of a Signaling Multi-Frame is input to the Frame Generator when Signaling Multi-
Frame is generated and coincides with the CRC Multi-Frame.
SIGMFI(b4, E1-045H) SIGMFE(b4, E1-044H)
2 The end of the first frame of a CRC-4 Multi-Frame is input to the Frame Generator when CRC Multi-Frame is
generated.
MFI(b2, E1-045H)
MFE(b4, E1-044H)
3 The end of the first frame of a CRC-4 Sub Multi-Frame is input to the Frame Generator when CRC Multi-Frame
is generated.
SMFI(b1, E1-045H)
SMFE(b4, E1-044H)
4 The boundary of a FAS is input to the Frame Generator when Basic Frame is generated.
FASI (b3, E1-045H)
FASE(b4, E1-044H)
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| IDT82V2108BBG | 功能描述:IC FRAMER T1/J1/E1 8CH 144-BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| IDT82V2108PX | 功能描述:IC FRAMER T1/J1/E1 8CH 128-PQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| IDT82V2108PX8 | 功能描述:IC FRAMER T1/J1/E1 8CH 128-PQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| IDT82V2108PXG | 功能描述:IC FRAMER T1/J1/E1 8CH 128-PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| IDT82V2108PXG8 | 功能描述:IC FRAMER T1/J1/E1 8CH 128-PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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