*Notes:
參數(shù)資料
型號(hào): IDT82V3001APVG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 16/28頁
文件大?。?/td> 0K
描述: IC PLL WAN W/SGL REF INP 56SSOP
標(biāo)準(zhǔn)包裝: 26
類型: 時(shí)鐘/頻率發(fā)生器
PLL:
主要目的: WAN
輸入: CMOS,TTL
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:14
差分 - 輸入:輸出: 無/無
頻率 - 最大: 32.768MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 56-SSOP
包裝: 管件
其它名稱: 82V3001APVG
IDT82V3001APVG-ND
TEST SPECIFICATIONS
23
October 15, 2008
IDT82V3001A
WAN PLL WITH SINGLE REFERENCE INPUT
*Notes:
Voltages are with respect to ground (VSS) unless otherwise stated.
Supply voltage and operating temperature are as per Recommended Operating Conditions.
Timing parameters are as per AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels
1.
Normal Mode selected.
2.
Holdover Mode selected.
3.
Freerun Mode selected.
4.
8 kHz Frequency Mode selected.
5.
1.544 MHz Frequency Mode selected.
6.
2.048 MHz Frequency Mode selected.
7.
Master clock input OSCi at 20 MHz ±0 ppm.
8.
Master clock input OSCi at 20 MHz ±32 ppm.
9.
Master clock input OSCi at 20 MHz ±100 ppm.
10. Selected reference input at
±0 ppm.
11. Selected reference input at
±32 ppm.
12. Selected reference input at
±100 ppm.
13. For Freerun Mode of
±0 ppm.
14. For Freerun Mode of
±32 ppm.
15. For Freerun Mode of
±100 ppm.
16. For capture range of
±230 ppm.
17. For capture range of
±198 ppm.
18. For capture range of
±130 ppm.
19. 25 pF capacitive load.
20. OSCi Master Clock jitter is less than 2 nspp, or 0.04 UIpp where 1 UIpp = 1/20 MHz.
21. Jitter on reference input is obtained at slightly higher input jitter amplitudes.
22. Applied jitter is sinusoidal.
23. Minimum applied input jitter magnitude to regain synchronization.
24. Loss of synchronization is obtained at slightly higher input jitter amplitudes.
25. Within 10 ms of the state, reference or input change.
26. 1 UIpp = 125 s for 8 kHz signals.
27. 1 UIpp = 648 ns for 1.544 MHz signals.
28. 1 UIpp = 488 ns for 2.048 MHz signals.
29. 1 UIpp = 323 ns for 3.088 MHz signals.
30. 1 UIpp = 244 ns for 4.096 MHz signals.
31. 1 UIpp = 122 ns for 8.192 MHz signals.
32. 1 UIpp = 61 ns for 16.484 MHz signals.
33. 1 UIpp = 30 ns for 32.968 MHz signals.
34. No filter.
35. 40 Hz to 100 kHz bandpass filter.
36. With respect to reference input signal frequency.
37. After chip reset or TIE reset.
38. Master clock duty 40% to 60%.
39. Prior to Holdover Mode, device as in Normal Mode and phase locked.
40. With input frequency offset of 100 ppm.
Table - 16 2.048 MHz Input Jitter Tolerance
Description
Min
Typ
Max
Units
Test Conditions / Notes*
Jitter tolerance for 1 Hz input
150
UIpp
1, 6, 7-12, 19-20, 22-24, 28
Jitter tolerance for 5 Hz input
140
UIpp
1, 6, 7-12, 19-20, 22-24, 28
Jitter tolerance for 20 Hz input
130
UIpp
1, 6, 7-12, 19-20, 22-24, 28
Jitter tolerance for 300 Hz input
40
UIpp
1, 6, 7-12, 19-20, 22-24, 28
Jitter tolerance for 400 Hz input
33
UIpp
1, 6, 7-12, 19-20, 22-24, 28
Jitter tolerance for 700 Hz input
18
UIpp
1, 6, 7-12, 19-20, 22-24, 28
Jitter tolerance for 2400 Hz input
5.5
UIpp
1, 6, 7-12, 19-20, 22-24, 28
Jitter tolerance for 10 kHz input
1.3
UIpp
1, 6, 7-12, 19-20, 22-24, 28
Jitter tolerance for 100 kHz input
0.4
UIpp
1, 6, 7-12, 19-20, 22-24, 28
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