- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9671 > IDT82V3001APVG (IDT, Integrated Device Technology Inc)IC PLL WAN W/SGL REF INP 56SSOP PDF資料下載
參數(shù)資料
| 型號(hào)： | IDT82V3001APVG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 26/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL WAN W/SGL REF INP 56SSOP |
| 標(biāo)準(zhǔn)包裝： | 26 |
| 類型： | 時(shí)鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | WAN |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:14 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 32.768MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-SSOP |
| 包裝： | 管件 |
| 其它名稱： | 82V3001APVG IDT82V3001APVG-ND |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)當(dāng)前第26頁(yè)第27頁(yè)第28頁(yè)
PIN DESCRIPTION
7
October 15, 2008
IDT82V3001A
WAN PLL WITH SINGLE REFERENCE INPUT
2
PIN DESCRIPTION
Table - 1 Pin Description
Name
Type
Pin
Number
Description
VSS
Power
12, 18, 27,
38, 47
Ground.
0 V. All VSS pins should be connected to the ground.
VDDA
Power
37, 48
3.3 V Analog Power Supply.
VDDD
Power
13, 19, 26 3.3 V Digital Power Supply.
OSCo
(CMOS) O
49
Oscillator Master Clock.
This pin is left unconnected.
OSCi
(CMOS) I
50
Oscillator Master Clock.
This pin is connected to a clock source.
Fref
I
5
Reference Input.
This is the input reference source (falling edge) used for synchronization. One of three possible frequencies (8 kHz, 1.544
MHz, or 2.048 MHz) may be used. The Fref pin is internally pulled up to VDDD.
F_sel1
I
10
Input Frequency Select 1.
This input, in conjunction with F_sel0, determines which of three possible frequencies (8 kHz, 1.544 MHz, or 2.048 MHz )
may be input to the Reference Input.
F_sel0
I
9
Input Frequency Select 0.
See above.
MODE_sel1
I
2
Mode/Control Select 1.
This input, in conjunction with MODE_sel0, determines the operation mode of the IDT82V3001A (Normal, Holdover or
Freerun) . The logic level at this input is gated in by the rising edge of F8o. This pin is internally pulled down to VSS. See
MODE_sel0
I
1
Mode/Control Select 0.
See above. The logic level at this input is gated in by the rising edge of F8o. This pin is internally pulled down to VSS.
RST
I4
Reset Input.
A logic low at this pin resets the IDT82V3001A. To ensure proper operation, the device must be reset after the frequency
of the input reference is changed and power-up. The RST pin should be held low for a minimum of 300 ns. While the RST
pin is low, all framing and clock outputs are at logic high.
TCLR
I3
TIE Circuit Reset.
Logic low at this input resets the TIE (Time Interval Error) control block, resulting in a realignment of output phase with
input phase. The TCLR pin should be held low for a minimum of 300 ns. This pin is internally pulled up to VDDD.
TIE_en
I
56
TIE Enable.
A logic high at this pin enables the TIE control block while a logic low at this pin disables the TIE control block. The logic
level at this input is gated in by the rising edge of F8o. This pin is internally pulled down to Vss.
FLOCK
I
45
Fast Lock Mode.
Set high to allow the DPLL to quickly lock to the input reference (less than 500 ms locking time).
LOCK
(CMOS) O
44
Lock Indicator.
This output goes high when the DPLL is frequency locked to the input reference.
HOLDOVER (CMOS) O
52
Holdover Indicator.
This output goes to a logic high whenever the DPLL goes into Holdover Mode.
NORMAL
(CMOS) O
46
Normal Indicator.
This output goes to a logic high whenever the DPLL goes into Normal Mode.
FREERUN (CMOS) O
51
Freerun Indicator.
This output goes to a logic high whenever the DPLL goes into Freerun Mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-B40-MW-F3 | CONVERTER MOD DC/DC 5V 100W |
| ICS874005AG-04LF | IC PCI EXPRSS/JITT ATTEN 24TSSOP |
| VE-B40-MW-F2 | CONVERTER MOD DC/DC 5V 100W |
| ICS8741004AGLF | IC PCI EXPRSS/JITT ATTEN 24TSSOP |
| ICS9DB306BLLF | IC JITTER ATTENUATOR 28TSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V3001APVG8 | 功能描述:IC PLL WAN W/SGL REF INP 56-SSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDT82V3002A | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL WITH DUAL REFERENCE INPUTS |
| IDT82V3002A_08 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL WITH DUAL REFERENCE INPUTS |
| IDT82V3002A-01PVG | 功能描述:IC PLL WAN T1/E1 56SSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDT82V3002A-01PVG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN T1/E1 56SSOP |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。