參數(shù)資料
型號(hào): IDT82V3001APVG
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 2/28頁(yè)
文件大小: 0K
描述: IC PLL WAN W/SGL REF INP 56SSOP
標(biāo)準(zhǔn)包裝: 26
類(lèi)型: 時(shí)鐘/頻率發(fā)生器
PLL:
主要目的: WAN
輸入: CMOS,TTL
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:14
差分 - 輸入:輸出: 無(wú)/無(wú)
頻率 - 最大: 32.768MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 56-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 56-SSOP
包裝: 管件
其它名稱(chēng): 82V3001APVG
IDT82V3001APVG-ND
FUNCTIONAL DESCRIPTION
10
October 15, 2008
IDT82V3001A
WAN PLL WITH SINGLE REFERENCE INPUT
3
FUNCTIONAL DESCRIPTION
The IDT82V3001A is a WAN PLL with single reference input,
providing timing (clock) and synchronization (framing) signals to
interface circuits for T1 and E1 Primary Rate Digital Transmission links.
See Figure - 1. The detail is described in the following sections.
3.1
STATE CONTROL CIRCUIT
The State Control Circuit is an important part of the IDT82V3001A.
As shown in Figure - 3, the State Control Circuit outputs signals to
enable/disable the TIE Control Block and control the operation mode of
the DPLL Block based on MODE_sel0 and MODE_sel1 and TIE_en
pins.
Figure - 3 State Control Block
The IDT82V3001A has three possible modes of operation: Normal,
Holdover and Freerun. The mode selection pins, MODE_sel1 and
MODE_sel0 select the operation mode. See Table - 2.
All state control changes occur synchronously on the rising edge of
F8o. As shown in Figure - 4, the operating mode can be changed from
one to another by the MODE_sel0 and MODE_sel1 pins, except the
mode changes between Normal (S1) and Auto-Holdover (S2). The
mode changes between Normal (S1) and Auto-Holdover (S2) are
triggered by the Invalid Input Reference Detection Circuit and irrelative
to the MODE_sel0 and MODE_sel1 pins. That is, at the stage of S1, the
operating mode will be changed automatically from Normal (S1) to Auto-
Holdover (S2) if an invalid input reference is detected (input reference is
out of the capture range). If the input reference becomes valid (within
the capture range), the operating mode will be changed back to Normal
(S1) automatically.
When the operating mode is changed from one to another, the TIE
control block will be disabled automatically as shown in Figure - 4,
except the change from Holdover (S3) or Auto-Holdover (S2) to Normal
(S1). In the case of changing from Holdover (S3) or Auto-Holdover (S2)
to Normal (S1), the TIE control block can be manually enabled or
disabled by the TIE_en pin, as required.
State Control Circuit
MODE_sel1 MODE_sel0
TIE_en
Output of the
Invalid Input
Signal Detection
F8o
TIE Block
Enable/Disable
DPLL Block
Mode Control
Table - 2 Operating Modes and Status
MODE_sel1
MODE_sel0
Mode
00
Normal
0
1
Holdover
1
0
Freerun
11
Reserved
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