參數(shù)資料
型號: IDT82V3155PVG8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 5 INVERTED OUTPUT(S), PDSO56
封裝: SSOP-56
文件頁數(shù): 14/30頁
文件大?。?/td> 406K
代理商: IDT82V3155PVG8
21
IDT82V3155 ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE
7.6
C155 (155.52 MHZ) INTRINSIC JITTER FILTERED
7.7
8 KHZ INPUT TO 8 KHZ OUTPUT JITTER TRANSFER
7.8
1.544 MHZ INPUT TO 1.544 MHZ OUTPUT JITTER TRANSFER
Description
Min.
Typ.
Max.
Units
Test Conditions / Notes
(see “Notes” on page 24)
Intrinsic jitter (500 Hz to 1.3 MHz filter)
0.4
0.5
nspp
1-15, 22-25, 39
Intrinsic jitter (65 kHz to 1.3 MHz filter)
0.2
0.3
nspp
1-15, 22-25, 39
Description
Min.
Typ.
Max.
Units
Test Conditions / Notes
(see “Notes” on page 24)
Jitter attenuation for 1 Hz@0.01 UIpp input
0
6
dB
1-3, 6, 10-15, 22-23, 25, 29, 40
Jitter attenuation for 1 Hz@0.54 UIpp input
6
16
dB
1-3, 6, 10-15, 22-23, 25, 29, 40
Jitter attenuation for 10 Hz@0.10 UIpp input
15
22
dB
1-3, 6, 10-15, 22-23, 25, 29, 40
Jitter attenuation for 60 Hz@0.10 UIpp input
32
38
dB
1-3, 6, 10-15, 22-23, 25, 29, 40
Jitter attenuation for 300 Hz@0.10 UIpp input
42
dB
1-3, 6, 10-15, 22-23, 25, 29, 40
Jitter attenuation for 3600 Hz@0.005 UIpp input
50
dB
1-3, 6, 10-15, 22-23, 25, 29, 40
Description
Min.
Typ.
Max.
Units
Test Conditions / Notes
(see “Notes” on page 24)
Jitter attenuation for 1 Hz@20 UIpp input
0
6
dB
1-3, 7, 10-15, 22-23, 25, 30, 40
Jitter attenuation for 1 Hz@104 UIpp input
6
16
dB
1-3, 7, 10-15, 22-23, 25, 30, 40
Jitter attenuation for 10 Hz@20 UIpp input
17
22
dB
1-3, 7, 10-15, 22-23, 25, 30, 40
Jitter attenuation for 60 Hz@20 UIpp input
33
38
dB
1-3, 7, 10-15, 22-23, 25, 30, 40
Jitter attenuation for 300 Hz@20 UIpp input
45
dB
1-3, 7, 10-15, 22-23, 25, 30, 40
Jitter attenuation for 10 kHz@0.3 UIpp input
48
dB
1-3, 7, 10-15, 22-23, 25, 30, 40
Jitter attenuation for 40 kHz@0.3 UIpp input
50
dB
1-3, 7, 10-15, 22-23, 25, 30, 40
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