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參數(shù)資料
| 型號(hào)： | IDT82V3155PVG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 5 INVERTED OUTPUT(S), PDSO56 |
| 封裝： | SSOP-56 |
| 文件頁數(shù)： | 4/30頁 |
| 文件大?。?/td> | 406K |
| 代理商： | IDT82V3155PVG8 |
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IDT82V3155 ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE
If the TIE Control Block is disabled manually or automatically, a
reference switch will result in a phase alignment between the input
signal and the output signal as shown in Figure - 6. The slope of the
phase adjustment is limited to 5 ns per 125 s.
Figure - 5 Reference Switch with TIE Control Block Enabled
Figure - 6 Reference Switch with TIE Control Block Disabled
2.7
DPLL BLOCK
As shown in Figure - 7, the DPLL Block consists of a Phase Detector,
a Limiter, a Loop Filter, a Digital Control Oscillator and Divider.
2.7.1
PHASE DETECTOR (PHD)
In the Normal mode, the Phase Detector compares the virtual
reference signal from the TIE Control Circuit with the feedback signal
from the Frequency Select Circuit, and outputs an error signal
corresponding to the phase difference. This error signal is sent to the
Limiter circuit for phase slope control.
In the Freerun or Holdover mode, the Frequency Select Circuit, the
Phase Detector and the Limiter are inactive, and the input reference
signal is not used.
Input Clock
Ref1
Ref2
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Output Clock
Input Clock
Ref1
Ref2
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Output Clock
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相關(guān)代理商/技術(shù)參數(shù) |
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| IDT82V32021NLGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:EBU WAN PLL |
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