參數(shù)資料
型號(hào)： IDT82V3155PVG8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 5 INVERTED OUTPUT(S), PDSO56
封裝： SSOP-56
文件頁(yè)數(shù)： 5/30頁(yè)
文件大?。?/td> 406K
代理商： IDT82V3155PVG8
13
IDT82V3155 ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE
2.7.2
LIMITER
The Limiter is used to limit the phase slope. It ensures that the
maximum output phase slope is limited to 5 ns per 125 s for all input
transient conditions. This well meets the AT&T TR62411 and Telcordia
GR-1244-CORE specifications, which specify the maximum phase slope
of 7.6 ns per 125 s and 81 ns per 1.326 ms respectively.
Figure - 7 DPLL Block Diagram
In the Normal mode, the Limiter receives the error signal from the
Phase Detector, limits the phase slope within 5 ns per 125 s and sends
the limited signal to the Loop Filter.
In the Fast Lock mode, the Limiter is disabled, and the DPLL locks to
the input reference within 500 ms, which is much shorter than that in the
Normal mode.
2.7.3
LOOP FILTER
The Loop Filter ensures that the jitter transfer meets the ETS 300
011 and AT&T TR62411 requirements. It works similarly to a first order
low pass filter with 2.1 Hz cutoff frequency for the four valid input
frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz).
The output of the Loop Filter goes to the Digital Control Oscillator
directly or through the Fraction blocks, in which E1, T1, C6 and C19
signals are generated.
2.7.4
FRACTION BLOCK
By applying some algorithms to the incoming E1 signal, the
Fraction_C19, Fraction_C6 and Fraction_T1 blocks generate C19, C6
and T1 signals respectively.
2.7.5
DIGITAL CONTROL OSCILLATOR (DCO)
In the Normal mode, the DCO receives four limited and filtered
signals from Loop Filter or Fraction blocks. Based on the values of the
received signals, the DCO generates four digital outputs: 19.44 MHz,
25.248 MHz, 32.768 MHz and 24.704 MHz for C19, C6, E1 and T1
dividers respectively.
In the Holdover mode, the DCO is running at the same frequency as
that generated by storage techniques.
In the Freerun mode, the DCO is running at the same frequency as
that of the master clock.
Dig
ital
Con
trol
Osci
llat
or
C32o
C16o
C8o
C4o
C2o
C3o
C6o
F0o
F8o
RSP
TSP
F16o
C1.5o
F32o
Output Interface
T1_Divider
E1_Divider
C6_Divider
Frequency
Selection
Circuit 1
Phase
Detector
Virtual Reference
Fraction_C6
Fraction_T1
24.704 MHz
32.768 MHz
25.248 MHz
Feedback Signal
Limiter
FLOCK
F1_sel1 F1_sel0
C19_Divider
155.52 MHz
F19o
C19o
APLL
19.44 MHz
Fraction_C19
C155NEG
C155POS
IN_sel
F0_sel1 F0_sel0
Frequency
Selection
Circuit 0
C2/C1.5
Loop Filter
Fx_sel1 Fx_sel0 (x = 0 or 1)
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