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參數(shù)資料
| 型號： | IDT82V3155PVG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 5 INVERTED OUTPUT(S), PDSO56 |
| 封裝： | SSOP-56 |
| 文件頁數(shù)： | 30/30頁 |
| 文件大?。?/td> | 406K |
| 代理商： | IDT82V3155PVG8 |
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9
IDT82V3155 ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE
2
FUNCTIONAL DESCRIPTION
The IDT82V3155 is a enhanced T1/E1/OC3 WAN PLL with dual
reference inputs, providing timing (clock) and synchronization (framing)
signals to interface circuits for multitrunk T1/E1 and STS3/OC3 links.
The details are described in the following sections.
2.1
STATE CONTROL CIRCUIT
The State Control Circuit is an important part in the IDT82V3155. It is
used to control the TIE block and the DPLL block as shown in Figure - 2.
The control is based on the result of Invalid Input Signal Detection and
the logic levels on the MODE_sel0, MODE_sel1, IN_sel and TIE_en
pins.
The IDT82V3155 can be operated in three different modes: Normal,
Holdover and Freerun. The operating mode is selected by the
MODE_sel1 and MODE_sel0 pins, as shown in Table - 1.
Figure - 3 shows the state control diagram. All state changes occur
synchronously on the rising edge of F8o. Three operating modes,
Normal (S1), Holdover (S3) and Freerun (S0) can be switched from one
to another by changing the logic levels on the MODE_sel0 and
MODE_sel1 pins.
Figure - 2 State Control Circuit
Figure - 3 State Control Diagram
Table - 1 Operating Modes Selection
Mode Selection Pins
Operating Mode
MODE_sel1
MODE_sel0
00
Normal
0
1
Holdover
1
0
Freerun
11
Reserved
State Control Circuit
MODE_sel1 MODE_sel0
TIE_en
Output of the
Invalid Input
Signal Detection
F8o
TIE Block
Enable/Disable
DPLL Block
Mode Control
IN_sel
S1
Normal
Mode_sel1 = 0
Mode_sel0 = 0
S3
Holdover
Mode_sel1 = 0
Mode_sel0 = 1
S0
Freerun
Mode_sel1 = 1
Mode_sel0 = 0
(Invalid Input Reference Signal)
(Valid Input Reference Signal)
Aut
o T
IE D
isab
le
Aut
o T
IE D
isab
le
TIE Enable (TIE_en = H)
AutoT
IE Dis
able
AutoTIE
Disable
Au
to
TIE
Dis
ab
le
TIE
Disa
ble
(TIE
_en
= L)
AutoT
IE Dis
able
TIE E
nable
(TIE_
en =
H)
Reset *
S4
Short Time Holdover
Mode_sel1 = 0
Mode_sel0 = 0
IN_
sel
Tra
nsie
nt
Auto
TIE
Dis
able
No IN
_sel T
ransie
nt
TIE E
nable
(TIE_
en =
H)
No
IN
_s
el
Tra
ns
ien
t
TIE
D
isa
ble
(T
IE
_e
n
=
L)
IN_s
el Tra
nsien
t
Auto
TIE D
isable
S2
Auto - Holdover
Mode_sel1 = 0
Mode_sel0 = 0
* Note: After reset, the Mode_sel1 and Mode_sel0 should be initially set to '10' or '00'.
Auto TIE Disable
(Valid Input Reference Signal)
TIE Disable (TIE_en = L)
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相關(guān)代理商/技術(shù)參數(shù) |
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| IDT82V3202 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:EBU WAN PLL |
| IDT82V32021 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:EBU WAN PLL |
| IDT82V32021NLBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:EBU WAN PLL |
| IDT82V32021NLGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:EBU WAN PLL |
| IDT82V3202EDGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:EBU WAN PLL |
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