參數(shù)資料
型號： IF180C52EXXX-L16:R
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44
文件頁數(shù)： 18/101頁
文件大?。?/td> 3398K
46
8168C-MCU Wireless-02/10
AT86RF212
compliant frames, refer to 5.2.3.2. All other procedures are exceptions for specific
operating modes or frame formats, refer to section 5.2.3.3.
In RX_AACK_ON state, the AT86RF212 listens for incoming frames. After detecting a
non-zero PHR, the AT86RF212 changes into BUSY_RX_AACK state and parses the
frame content of the MAC header (MHR), refer to section 6.1.2. If the content of the
MAC addressing fields of the received frame passes the frame filter, an address match
interrupt IRQ_5 (AMI) is issued. The reference address values are to be stored in
registers 0x20 – 0x2B (Short address, PAN ID, and IEEE address). The Frame Filter
operations are described in detail in section 6.2.
Generally, at nodes configured as a normal device or PAN coordinator, a frame is
indicated by interrupt IRQ_3 (TRX_END) if the frame passes the Frame Filter and the
FCS is valid. The interrupt is issued after the completion of the frame reception. The
microcontroller can then read the frame data. An exception applies if promiscuous
mode is enabled, see section 5.2.3.2. In that case, an interrupt IRQ_3 is issued for all
frames.
During reception, the AT86RF212 parses bit 5 (ACK Request) of the frame control field
of the received data or MAC command frame to check if an acknowledgement (ACK)
response is expected. In that case and if the frame matches the third level filtering rules
(see IEEE 802.15.4-2006, section 7.5.6.2), the radio transceiver automatically
generates and transmits an ACK frame and proceeds back to RX_AACK_ON state.
By default, the acknowledgment frame is transmitted aTurnaroundTime (12 symbols;
see IEEE 802.15.4-2006, section 6.4.1) after the reception of the last symbol of a data
or MAC command frame. Optionally, for non-compliant networks, this delay can be
reduced to 2 symbols by register bit AACK_ACK_TIME (register 0x2E, XAH_CTRL_1).
The content of the “Frame Pending” subfield of the ACK response is set according to
register bit AACK_SET_PD (register 0x2E, CSMA_SEED_1). The sequence number is
copied from the received frame accordingly.
If the register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1) is set, no
acknowledgement frame is sent, even if requested.
For slotted operation, the start of the transmission of acknowledgement frames is
controlled by pin 11 (SLP_TR), refer to 5.2.3.5.
The status of the RX_AACK transaction is indicated by register subfield
TRAC_STATUS (register 0x02, TRX_STATE). Table 5-7 lists corresponding values.
Table 5-7. RX_AACK interpretation of TRAC_STATUS Register Bits
Value
Name
Description
0
SUCCESS
The transaction has finished with success
2
SUCCESS_WAIT_FOR_ACK
The transaction either waits aTurnaroundTime
until the ACK is transmitted or expects the
rising edge on pin 11 (SLP_TR) to start the
transmission (slotted operation)
7
INVALID
Default value when RX_AACK transaction is
invoked
Note that generally the AT86RF212 PHY modes as well as the Extended Feature Set
work independent from RX_AACK Extended Operating Mode.
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IF180C52-L16 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
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IF180C52T-16 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
IF180C52T-20 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
IF180C52T-25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
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