參數(shù)資料
型號： IF180C52EXXX-L16:R
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44
文件頁數(shù)： 6/101頁
文件大小： 3398K
AT86RF212
(parameter 10.4.12). During reset, the microcontroller has to set the radio transceiver
control pins SLP_TR and /SEL to their default values.
An overview of the register reset values is provided in Table 11-2.
5.1.3 Interrupt Handling
All interrupts provided by the AT86RF212 (see Table 4-15) are supported in Basic
Operating Mode. For example, interrupts are provided to observe the status of radio
transceiver RX and TX operations.
When being in receive mode, IRQ_2 (RX_START) indicates the detection of a non-zero
PHR first, IRQ_5 (AMI) an address match, and IRQ_3 (TRX_END) the completion of
the frame reception. During transmission, IRQ_3 (TRX_END) indicates the completion
of the frame transmission.
Figure 5-2 shows an example for a transmit/receive transaction between two devices
and the related interrupt events in Basic Operating Mode. Device 1 transmits a frame
containing a MAC header, MAC payload, and a valid FCS. The end of the frame
transmission is indicated by IRQ_3 (TRX_END).
The frame is received by Device 2. Interrupt IRQ_2 (RX_START) indicates the
detection of a valid PHR field and IRQ_3 (TRX_END) the completion of the frame
reception. If the frame passes the Frame Filter (refer to 6.2), an address match interrupt
IRQ_5 (AMI) is issued after the reception of the MAC header (MHR).
Processing delay tIRQ is a typical value, refer to section 10.4.
Figure 5-2. Timing of RX_START, AMI, and TRX_END Interrupts in Basic Operating Mode for O-QPSK 250 kbit/s Mode
128
160
192
0
192+(m+n+2) 32 Time [μs]
RX
(De
vic
e2)
IRQ_2 (RX_START)
tIRQ
RX_ON
IRQ
State
Interrupt latency
TRX_END
IRQ_5 (AMI)
tIRQ
BUSY_RX
IRQ_3 (TRX_END)
TX
(D
ev
ic
e1
)
PLL_ON
BUSY_TX
PLL_ON
IRQ
SLP_TR
State
Processing Delay
Fra
m
e
on
A
ir
Preamble
SFD
PHR
MSDU
41
1
m
Number of Octets
Frame Content
MHR
FCS
2
tTR10
-tTR10
n
5.1.4 Timing
The following paragraphs depict state transitions and their timing properties. Timings
are explained in Table 5-1 and section 10.4.
35
8168C-MCU Wireless-02/10
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