參數(shù)資料
型號(hào)： INTEL82802AB
廠商： Intel Corp.
英文描述： Firmware Hub (FWH)
中文描述： 固件集線器（固件樞紐）
文件頁(yè)數(shù)： 17/53頁(yè)
文件大?。?/td> 471K
代理商： INTEL82802AB
Intel
82802AB/AC Firmware Hub
R
Datasheet
17
3.
Interface Operation Description
3.1.
Read
Memory information, identifier codes, GPI registers or the status register can be read, regardless of the
V
PP
voltage. Commands using the read mode include: reading memory from the array, reading the
identifier codes, reading the status register, reading the lock bit registers, reading the random number
generator, reading the GPI registers, and reading the RNG status register. Upon initial device power-up
or after exit from reset, the device automatically resets to read array mode.
3.2.
Write
Writes to the memory array’s CUI are initiating by issuing a write through the Intel FWH interface. (See
the following information on timing and Intel FWH cycle write protocol specifics.) The CUI does not
occupy a single, specific memory location—any valid address may be given. However, certain
commands, such as block erase, require the address be within the range of the desired address block.
3.3.
Output Disable
When the Intel FWH is not selected through a FWH read or write cycle, the Intel FWH interface outputs
(FWH[3:0]) are disabled and is placed in a high-impedance state.
3.4.
Reset
RST# or INIT# at V
IL
initiates a device reset. In the read mode, RST# or INIT# low deselects the
memory, places output drivers in a high-impedance state, and turns off all internal circuits. RST# or
INIT# must be held low for time t
PLPH
(A/A Mux and FWH operation). The Intel FWH resets to read
array mode upon return from reset, and all blocks are set to default (locked) status (see 4.9.1), regardless
of their locked state prior to reset.
During block erase or program, driving RST# or INIT# low will abort the operation underway, in
addition to causing a reset latency. Memory contents being altered are no longer valid, since the data may
be partially erased or programmed.
It is important to assert RST# or INIT# during system reset. When the system comes out of reset, it will
expect to read from the memory array of the device. If a system reset occurs with no FWH reset—this is
hardware dependent—it is possible that proper processor initialization will not occur. (The Intel FWH
memory may be providing status information instead of memory array data.)
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