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參數(shù)資料
| 型號： | INTEL82802AB |
| 廠商： | Intel Corp. |
| 英文描述： | Firmware Hub (FWH) |
| 中文描述： | 固件集線器（固件樞紐） |
| 文件頁數(shù)： | 44/53頁 |
| 文件大?。?/td> | 471K |
| 代理商： | INTEL82802AB |
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Intel
82802AB/AC Firmware Hub
R
44
Datasheet
5.4.1.6.
Abort Operations
FWH4 active (low) indicates either that a START cycle will eventually occur or that an abort is in
progress. In either case, if FWH4 is asserted, the Intel FWH will “immediately” tri-state its outputs and
the FWH state machine will reset.
During a write cycle, there is a possibility that an internal flash write or erase operation is in progress (or
has just been initiated). If FWH4 is asserted during this time frame, the internal operation will
not
abort.
The software must send an explicit flash command to terminate or suspend the operation.
The internal FWH state machine will not initiate a flash write or erase operation until it has received the
last data nibble from the chipset. This means that FWH4 can be asserted as late as this cycle (“cycle 12”)
and no internal flash operation will be attempted. However, since the Intel FWH will start “processing”
incoming data before it generates its SYNC field, it should be considered a
non-buffered peripheral
device.
5.4.1.7.
Intel FWH Cycle Timing Information
Refer to Figure Figure 12 and Figure 13.
Table 18.
Signal Timing Parameters
Symbol
“PCI Symbol”
Parameter
Condition
Min.
Max.
Units
Notes
TCHQV
t
val
CLK to data out
2
11
ns
1
TCHQX
t
on
CLK to active
(float to active delay)
2
ns
2
TCHQZ
t
off
CLK to inactive
(active to float delay)
28
ns
2
TAVCH
TDVCH
t
su
Input setup time
7
ns
3
TCHAX
TCHDX
t
h
Input hold time
0
ns
3
TVSPL
t
rst
Reset active time after
power stable
1
ms
TCSPL
t
rst-clk
Reset active time after
CLK stable
100
μ
s
TPLQZ
t
rst-off
Reset active to output
float delay
48
ns
2
Note:
1. Minimum and maximum times have different loads. See the PCI specification.
2. For purposes of active/float timing measurements, the Hi-Z or “off” state is defined as the state
where the total current delivered through the component pin is less than or equal to the leakage
current specification.
3. This parameter applies to any input type (excluding CLK).
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