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參數(shù)資料
| 型號： | INTEL82802AB |
| 廠商： | Intel Corp. |
| 英文描述： | Firmware Hub (FWH) |
| 中文描述： | 固件集線器（固件樞紐） |
| 文件頁數(shù)： | 20/53頁 |
| 文件大?。?/td> | 471K |
| 代理商： | INTEL82802AB |
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Intel
82802AB/AC Firmware Hub
R
20
Datasheet
Table 3.
Status Register Definition
7
6
5
4
3
2
1
0
WSMS
ESS
ES
PS
VPPS
PSS
DPS
R
Bit
Description
7
Write State Machine Status (SR.7).
Check SR.7 to determine block erase or program completion.
SR.6–0 are invalid while SR.7 = 0.
1 = Ready
0 = Busy
6
Erase Suspend Status (SR.6).
1 = Block erase suspended
0 = Block erase in progress/completed
5
Erase Status (SR.5).
If both SR.5 and SR.4 are 1s after a block erase attempt, an improper command
sequence was entered.
1 = Error in block erasure
0 = Successful block erase
4
Program Status (SR.4).
1 = Error in program
0 = Successful program
3
V
PP
Status (SR.3).
SR.3 does not provide a continuous indication of V
PP
level. The WSM interrogates
and indicates the V
PP
level only after a block erase or program operation. SR.3 is not guaranteed to
reports accurate feedback only when V
PP
≠
V
PPH1/2
.
1 = V
PP
low detect, operation abort
0 = V
PP
OK
2
Program Suspend Status (SR.2).
1 = Program suspended
0 = Program in progress/completed
1
Device Protect Status (SR.1).
SR.1 does not provide a continuous indication of write-lock bit, TBL# pin
or WP# pin values. The WSM interrogates the write-lock bit, TBL# pin or WP# pin only after a block
erase or program operation. Depending on the attempted operation, it informs the system whether or not
the selected block is locked.
1 = Write-lock bit, TBL# pin, or WP# pin Detected, operation abort
0 = Unlock
0
Reserved for future enhancements (SR.0).
SR.0 is reserved for future use and should be masked out
when polling the status register.
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