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參數(shù)資料
| 型號： | IS41LV16100A-60TL |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| 中文描述： | 1M X 16 EDO DRAM, 60 ns, PDSO44 |
| 封裝： | 0.400 INCH, TSOP2-50/44 |
| 文件頁數(shù)： | 4/22頁 |
| 文件大?。?/td> | 144K |
| 代理商： | IS41LV16100A-60TL |
IS41LV16100A
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
03/02/05
ISSI
Functional Description
The IS41LV16100A is a CMOS DRAM optimized for
high-
speed
bandwidth,
low power applications. During READ or
WRITE cycles, each bit is uniquely addressed through the
16 address bits. These are entered ten bits (A0-A9) at time.
The row address is latched by the Row Address Strobe
(
RAS
). The column address is latched by the Column
Address Strobe (
CAS
).
RAS
is used to latch the first nine bits
and
CAS
is used to latch the latter nine bits.
The IS41LV16100A has two
CAS
controls,
LCAS
and
UCAS
.
The
LCAS
and
UCAS
inputs internally generates a
CAS
signal functioning in an identical manner to the single
CAS
input on the other 1M x 16 DRAMs.
The key difference is that
each
CAS
controls its corresponding I/O tristate logic (
in
conjunction with
OE
and
WE
and
RAS
).
LCAS
controls I/O0
through I/O7 and
UCAS
controls I/O8 through I/O15.
The IS41LV16100A
CAS
function is determined by the first
CAS
(
LCAS
or
UCAS
) transitioning LOW and the last
transitioning back HIGH. The two
CAS
controls give the
IS41LV16100A both BYTE READ and BYTE WRITE cycle
capabilities.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE
,
whichever occurs last, while holding
WE
HIGH. The column
address must be held for a minimum time specified by t
AR
.
Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OEA
are all satisfied. As a result, the access time is dependent
on the timing relationships between these parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE
,
whichever occurs last. The input data must be valid at or
before the falling edge of
CAS
or
WE
, whichever occurs first.
Auto Refresh Cycle
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1,024 row addresses (A0 through A9)
with
RAS
at least once every 128 ms. Any read, write, read-
modify-write or
RAS
-only cycle refreshes the addressed row.
2. Using a
CAS
-before-
RAS
refresh cycle.
CAS
-before-
RAS
refresh is activated by the falling edge of
RAS
,
while holding
CAS
LOW. In
CAS
-before-
RAS
refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS
-before-
RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 1,024 columns within
a selected row to be randomly accessed at a high data rate.
In EDO page mode read cycle, the data-out is held to the
next
CAS
cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the
CAS
cycle time becomes shorter. There-
fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the
CAS
cycle time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS
cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one
RAS
cycle, but the performance is
equivalent to that of the fast page mode in that case.
Power-On
After application of the V
DD
supply, an initial pause of
200 μs is required followed by a minimum of eight
initialization cycles (any combination of cycles contain-
ing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
DD
or be held at a valid V
IH
to avoid current surges.
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| IS41LV16100A-60TLI | 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IS41LV16100A-60TLI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41LV16100B | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41LV16100B-50K | 功能描述:動態(tài)隨機存取存儲器 16M 1Mx16 50ns RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS41LV16100B-50KI | 功能描述:動態(tài)隨機存取存儲器 16M 1Mx16 50ns RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS41LV16100B-50KI-TR | 功能描述:動態(tài)隨機存取存儲器 16M 1Mx16 50ns RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
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