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參數(shù)資料
| 型號： | IS43R16160A |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 16Meg x 16 256-MBIT DDR SDRAM |
| 中文描述： | 16Meg × 16 256兆位DDR SDRAM的 |
| 文件頁數(shù)： | 9/56頁 |
| 文件大?。?/td> | 792K |
| 代理商： | IS43R16160A |
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00B
11/28/05
9
ISSI
IS43R16160A
Output Data (DQ) and Data Strobe (DQS) Timing Relative to the Clock (CK)
During Read Cycles
The minimum time during which the output data (DQ) is valid is critical for the receiving device (i.e., a mem-
ory controller device). This also applies to the data strobe during the read cycle since it is tightly coupled to
the output data. The minimum data output valid time (t
DV
) and minimum data strobe valid time (t
DQSV
) are de-
rived from the minimum clock high/low time minus a margin for variation in data access and hold time due to
DLL jitter and power supply noise.
(CAS Latency = 2.5; Burst Length = 4)
T0
T1
T2
T3
T4
NOP
NOP
NOP
D
0
CK, CK
Command
DQS
DQ
D
2
t
DQSCK
(max)
t
DQSCK
(min)
D
1
t
AC
(min)
t
AC
(max)
D
3
READ
NOP
Read Preamble and Postamble Operation
Prior to a burst of read data and given that the controller is not currently in burst read mode, the data strobe
signal (DQS), must transition from Hi-Z to a valid logic low. The is referred to as the data strobe “read pream-
ble” (t
). This transition from Hi-Z to logic low nominally happens one clock cycle prior to the first edge of
valid data.
Once the burst of read data is concluded and given that no subsequent burst read operations are initiated,
the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data
strobe “read postamble” (t
RPST
). This transition happens nominally one-half clock period after the last edge of
valid data.
Consecutive or “gapless” burst read operations are possible from the same DDR SDRAM device with no
requirement for a data strobe “read” preamble or postamble in between the groups of burst data. The data
strobe read preamble is required before the DDR device drives the first output data off chip. Similarly, the
data strobe postamble is initiated when the device stops driving DQ data at the termination of read burst cycles.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS43R16320A | 32Meg x 16 512-MBIT DDR SDRAM |
| IS43R16320A-6TL | 32Meg x 16 512-MBIT DDR SDRAM |
| IS43R16800A-6 | 8Meg x 16 128-MBIT DDR SDRAM |
| IS43R16800A-6T | 8Meg x 16 128-MBIT DDR SDRAM |
| IS43R16800A-6TL | 8Meg x 16 128-MBIT DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS43R16160A-5T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 16 256-MBIT DDR SDRAM |
| IS43R16160A-5TL | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 16 256-MBIT DDR SDRAM |
| IS43R16160A-6T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 16 256-MBIT DDR SDRAM |
| IS43R16160B | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:32Mx8, 16Mx16 256Mb DDR Synchronous DRAM |
| IS43R16160B-5BI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:32Mx8, 16Mx16 256Mb DDR Synchronous DRAM |
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