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參數(shù)資料
| 型號(hào)： | IS43R32400A-5B |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 4Meg x 32 128-MBIT DDR SDRAM |
| 中文描述： | 4M X 32 DDR DRAM, 0.7 ns, PBGA144 |
| 封裝： | 12 X 12 MM, 0.80 MM PITCH, MINI, FBGA-144 |
| 文件頁數(shù)： | 4/25頁 |
| 文件大小： | 1295K |
| 代理商： | IS43R32400A-5B |
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00D
02/15/06
ISSI
IS43R32400A
PIN FUNCTIONS
Symbol
A0-A11
Type
Input Pin
Function (In Detail)
Address inputs are sampled during several commands. During an Active
command, A0-A11 select a row to open. During a Read or Write command,
A0-A7 select a starting column for a burst. During a Pre-charge command,
A8 determines whether all banks are to be pre-charged, or a single bank.
During a Load Mode Register command, the address inputs select an
operating mode.
Bank Address inputs are used to select a bank during Active, Pre-charge,
Read, or Write commands. During a Load Mode Register command, BA0
and BA1 are used to select between the Base or Extended Mode Register
CAS
is Column Access Strobe, which is an input to the device command
along with
RAS
and
WE
. See “Command Truth Table” for details.
Clock Enable: CKE High activates and CKE Low de-activates internal clock
signals and input/output buffers. When CKE goes Low, it can allow Self
Refresh, Pre-charge Power Down, and Active Power Down. CKE must be
High during entire Read and Write accesses. Input buffers except CLK,
CLK
, and CKE are disabled during Power Down. CKE uses an SSTL 2
input, but will detect a LVCMOS Low level after VDD is applied.
All address and command inputs are sampled on the rising edge of the
clock input CLK and the falling edge of the differential clock input
CLK
.
Output data is referenced from the crossings of CLK and
CLK
.
The Chip Select input enables the Command Decoding block of the device.
When
CS
is disabled, a NOP occurs. See “Command Truth Table” for
details. Multiple DDR SDRAM devices can be managed with
CS
.
These are the Data Mask inputs. During a Write operation, the Data Mask
input allows masking of the data bus. DM is sampled on each edge of DQS.
There are four Data Mask input pins for the x32 DDR SDRAM. Each input
applies to DQ0-DQ7, DQ8-DQ15, DQ16-DQ23, or DQ24-DQ31.
These are the Data Strobe inputs. The Data Strobe is used for data capture.
During a Read operation, the DQS output signal from the device is edge-
aligned with valid data on the data bus. During a Write operation, the DQS
input should be issued to the DDR SDRAM device when the input values on
DQ inputs are stable. There are four Data Strobe pins for the x32 DDR
SDRAM. Each of the four Data Strobe pins applies to DQ0-DQ7, DQ8-
DQ15, DQ16-DQ23, or DQ24-DQ31.
The pins DQ0 to DQ31 represent the data bus. For Write operations, the
data bus is sampled on Data Strobe. For Read operations, the data bus is
sampled on the crossings of CK and
CK
.
No Connect: This pin should be left floating. These pins could be used for
256Mbit or higher density DDR SDRAM.
RAS
is Row Access Strobe, which is an input to the device command
along with
CAS
and
WE
. See “Command Truth Table” for details.
WE
is Write Enable, which is an input to the device command along with
RAS
and
CAS
. See “Command Truth Table” for details.
VDDQ is the output buffer power supply.
VDD is the device power supply.
VREF is the reference voltage for SSTL 2.
VSSQ is the output buffer ground.
VSS is the device ground.
BA0, BA1
Input Pin
CAS
Input Pin
CKE
Input Pin
CLK,
CLK
Input Pin
CS
Input Pin
DM0-DM3
Input Pin
DQS0-DQS3
Input/Output Pin
DQ0-DQ31
Input/Output Pin
NC
—
RAS
Input Pin
WE
Input Pin
VDDQ
VDD
VREF
VSSQ
VSS
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS43R32400A-5BL | 4Meg x 32 128-MBIT DDR SDRAM |
| IS43R32400A-6B | 4Meg x 32 128-MBIT DDR SDRAM |
| IS43R32400A-6BI | 4Meg x 32 128-MBIT DDR SDRAM |
| IS43R32400A-6BL | 4Meg x 32 128-MBIT DDR SDRAM |
| IS43R32400A-6BLI | 4Meg x 32 128-MBIT DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS43R32400A-5BL | 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M 2.5v 4Mx32 400MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS43R32400A-5BL-TR | 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M 2.5v 4Mx32 400MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS43R32400A-5B-TR | 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M 2.5v 4Mx32 400MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS43R32400A-6B | 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M 2.5v 4Mx32 333MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS43R32400A-6BI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:4Meg x 32 128-MBIT DDR SDRAM |
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