參數(shù)資料
型號(hào): IS61LV632A
廠商: Integrated Silicon Solution, Inc.
英文描述: 32K x 32 Synchronous Fast SRAM(32K x 32 同步快速靜態(tài)RAM)
中文描述: 32K的× 32同步快速靜態(tài)存儲(chǔ)器(32K的× 32同步快速靜態(tài)內(nèi)存)
文件頁數(shù): 14/16頁
文件大?。?/td> 176K
代理商: IS61LV632A
ISSI
14
Integrated Silicon Solution, Inc.
PRELIMINARY
SR017-1C
05/18/98
IS61LV632A
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
-4
-5
-6
-7
-8
Symbol
Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Min.
Max.
Unit
t
KC
Cycle Time
8
10
12
13
15
ns
t
KH
Clock High Time
4
4
4
6
6
ns
t
KL
Clock Low Time
4
4
4
6
6
ns
t
KQ
Clock Access Time
4
5
6
7
8
ns
t
KQX
(4)
Clock High to
Output Invalid
1.5
1.5
2
2
2
ns
t
KQLZ
(4,5)
Clock High to
Output Low-Z
0
0
0
0
0
ns
t
KQHZ
(4,5)
Clock High to
Output High-Z
1.5
4
1.5
5
1.5
6
2
6
2
6
ns
t
OEQ
Output Enable to
Output Valid
4.5
5
6
6
6
ns
t
OEQX
(4)
Output Disable to
Output Invalid
0
0
0
0
0
ns
t
OELZ
(4,5)
Output Enable to
Output Low-Z
0
0
0
0
0
ns
t
OEHZ
(4,5)
Output Disable to
Output High-Z
4.5
4.8
6
6
6
ns
t
AS
Address Setup Time
2.5
2.5
2.5
2.5
2.5
ns
t
SS
Address Status
Setup Time
2.5
2.5
2.5
2.5
2.5
ns
t
CES
Chip Enable Setup Time 2.5
2.5
2.5
2.5
2.5
ns
t
AH
Address Hold Time
0.5
0.5
0.5
0.5
0.5
ns
t
SH
Address Status
Hold Time
0.5
0.5
0.5
0.5
0.5
ns
t
CEH
Chip Enable Hold Time
0.5
0.5
0.5
0.5
0.5
ns
t
ZZS
ZZ Standby
(1)
2
2
2
2
2
cyc
t
ZZREC
ZZ Recovery
(2)
2
2
2
2
2
cyc
t
CFG
Configuration Setup
(3)
25
35
45
52
60
ns
Notes:
1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
2.
ADSC
and
ADSP
must not be asserted for at least 2 cyc after leaving ZZ state.
3. Configuration signal MODE is static and must not change during normal operation.
4. Guaranteed but not 100% tested. This parameter is periodically sampled.
5. Tested with load in Figure 2.
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