參數(shù)資料
型號: IS61LV632A
廠商: Integrated Silicon Solution, Inc.
英文描述: 32K x 32 Synchronous Fast SRAM(32K x 32 同步快速靜態(tài)RAM)
中文描述: 32K的× 32同步快速靜態(tài)存儲器(32K的× 32同步快速靜態(tài)內(nèi)存)
文件頁數(shù): 8/16頁
文件大小: 176K
代理商: IS61LV632A
ISSI
8
Integrated Silicon Solution, Inc.
PRELIMINARY
SR017-1C
05/18/98
IS61LV632A
READ CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
-4
-5
-6
-7
-8
Symbol
Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Min.
Max.
Unit
t
KC
Cycle Time
8
10
12
13
15
ns
t
KH
Clock High Time
4
4
4
6
6
ns
t
KL
Clock Low Time
4
4
4
6
6
ns
t
KQ
Clock Access Time
4
5
6
7
8
ns
t
KQX
(2)
Clock High to
Output Invalid
1.5
1.5
2
2
2
ns
t
KQLZ
(2,3)
Clock High to
Output Low-Z
0
0
0
0
0
ns
t
KQHZ
(2,3)
Clock High to
Output High-Z
1.5
4
1.5
5
2
6
2
6
2
6
ns
t
OEQ
Output Enable to
Output Valid
4
5
6
6
6
ns
t
OEQX
(2)
Output Disable to
Output Invalid
0
0
0
0
0
ns
t
OELZ
(2,3)
Output Enable to
Output Low-Z
0
0
0
0
0
ns
t
OEHZ
(2,3)
Output Disable to
Output High-Z
4.5
4.8
6
6
6
ns
t
AS
Address Setup Time
2.5
2.5
2.5
2.5
2.5
ns
t
SS
Address Status
Setup Time
2.5
2.5
2.5
2.5
2.5
ns
t
WS
Write Setup Time
2.5
2.5
2.5
2.5
2.5
ns
t
CES
Chip Enable Setup Time 2.5
2.5
2.5
2.5
2.5
ns
t
AVS
Address Advance
Setup Time
2.5
2.5
2.5
2.5
2.5
ns
t
AH
Address Hold Time
0.5
0.5
0.5
0.5
0.5
ns
t
SH
Address Status
Hold Time
0.5
0.5
0.5
0.5
0.5
ns
t
WH
Write Hold Time
0.5
0.5
0.5
0.5
0.5
ns
t
CEH
Chip Enable Hold Time
0.5
0.5
0.5
0.5
0.5
ns
t
AVH
Address Advance
Hold Time
0.5
0.5
0.5
0.5
0.5
ns
t
CFG
Configuration Setup
(1)
35
35
45
66.7
80
ns
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with the load in Figure 2.
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