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| 型號： | IS80C286-20 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 13/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPU 16BIT 5V 20MHZ 68-PLCC |
| 標準包裝： | 18 |
| 處理器類型： | 80C286 16-位 |
| 速度： | 20MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應商設備封裝： | 68-PLCC（24.23x24.23） |
| 包裝： | 管件 |
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20
Segment Descriptor Cache Registers
A segment descriptor cache register is assigned to each of
the four segment registers (CS, SS, DS, ES). Segment
descriptors are automatically loaded (cached) into a seg-
ment descriptor cache register (Figure 12) whenever the
associated segment register is loaded with a selector.
Only segment descriptors may be loaded into segment
descriptor cache registers. Once loaded, all references to
that segment of memory use the cached descriptor informa-
tion instead of reaccessing the descriptor. The descriptor
cache registers are not visible to programs. No instructions
exist to store their contents. They only change when a seg-
ment register is loaded.
Selector Fields
A protected mode selector has three fields: descriptor entry
index, local or global descriptor table indicator (TI), and selec-
tor privilege (RPL) as shown in Figure 13. These fields select
one of two memory based tables of descriptors, select the
appropriate table entry and allow high-speed testing of the
selector's privilege attribute (refer to privilege discussion
below).
Local and Global Descriptor Tables
Two tables of descriptors, called descriptor tables, contain all
descriptors accessible by a task at any given time. A descriptor
table is a linear array of up to 8192 descriptors. The upper 13
bits of the selector value are an index into a descriptor table.
Each table has a 24-bit base register to locate the descriptor
table in physical memory and a 16-bit limit register that confine
descriptor access to the defined limits of the table as shown in
Figure 14. A restartable exception (13) will occur if an attempt is
made to reference a descriptor outside the table limits.
One table, called the Global Descriptor table (GDT), con-
tains descriptors available to all tasks. The other table,
called the Local Descriptor Table (LDT), contains descriptors
that can be private to a task. Each task may have its own pri-
vate LDT. The GDT may contain all descriptor types except
interrupt and trap descriptors. The LDT may contain only
segment, task gate, and call gate descriptors. A segment
cannot be accessed by a task if its segment descriptor does
not exist in either descriptor table at the time of access.
TABLE 12. GATE DESCRIPTOR FORMAT FIELD
NAME
VALUE
DESCRIPTION
TYPE
4
Call Gate
5
Task Gate
6
Interrupt Gate
7
Trap Gate
P
0
Descriptor Contents are not valid
1
Descriptor Contents are valid
DPL
0 - 3
Descriptor Privilege Level
WORD
COUNT
0 - 31
Number of words to copy from callers
stack to called procedures stack. Only
used with call gate.
DESTINATION
SELECTOR
16-Bit
Selector
Selector to the target code segment
(call, interrupt or selector Trap Gate).
Selector to the target task state seg-
ment (Task Gate).
DESTINATION
OFFSET
16-Bit
Offset
Entry point within the target code seg-
ment
RESERVED
PDPL 0
TYPE
DESTINATION SELECTOR 15 - 0
DESTINATION OFFSET 15 - 0
15
70 7
7
80
0
+6
+4
+2
0
+7
+5
+3
+1
MUST BE SET TO 0 FOR COMPATIBILITY WITH FUTURE UPGRADES
XX X
XX
WORD COUNT
4 - 0
FIGURE 11. GATE DESCRIPTOR
BITS
NAME
FUNCTION
1 - 0
Requested Privilege Level
(RPL)
Indicates Selector Privilege
Level Desired
2
Table Indicator (TI)
TI = 0 Use Global Descrip-
tor Table (GDT)
TI = 1 Use Local Descriptor
Table (LDT)
15 - 3 Index
Select Descriptor Entry In
Table
FIGURE 13. SELECTOR FIELDS
PROGRAM VISIBLE
SEGMENT SELECTORS
CS
DS
SS
ES
15
0
SEGMENT REGISTERS
(LOADED BY PROGRAM)
SEGMENT SIZE
SEGMENT PHYSICAL
BASE ADDRESS
ACCESS
RIGHTS
PROGRAM INVISIBLE
47
40 39
16 15
0
SEGMENT DESCRIPTOR CACHE REGISTERS
(AUTOMATICALLY LOADED BY CPU)
FIGURE 12. DESCRIPTOR CACHE REGISTERS
INDEX
RPL
TI
15
8 7
2 1 0
SELECTOR
80C286
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