參數(shù)資料
型號(hào)： IS80C286-20
廠商： Intersil
文件頁(yè)數(shù)： 32/60頁(yè)
文件大?。?/td> 0K
描述： IC CPU 16BIT 5V 20MHZ 68-PLCC
標(biāo)準(zhǔn)包裝： 18
處理器類型： 80C286 16-位
速度： 20MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 68-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 68-PLCC（24.23x24.23）
包裝： 管件
38
NOTES:
18. Data is ignored.
19. First INTA cycle should have at least one wait state inserted to meet 82C59A minimum INTA pulse width.
20. Second INTA cycle must have at least one wait state inserted since the CPA will not drive A23-A0, BHE, and LOCK until after the first TC
state. The CPU imposed one/clock delay prevents has contention between cascade address buffer being disabled by MCE
↓ and address
outputs.
21. Without the wait state, the 80C286 address will not be valid for a memory cycle started immediately after the second INTA cycle. The
82C59A also requires one wait state for minimum INTA pulse width.
22. LOCK is active for the first INTA cycle to prevent the 82289 from releasing the bus between INTA cycles in a multi-master system. LOCK
is also active for the second INTA cycle.
23. A23-A0 exits three-state OFF during φ2 of the second TC in the INTA cycle.
FIGURE 29. INTERRUPT ACKNOWLEDGE SEQUENCE
TC
φ2
φ1
INTA CYCLE 1
TS
φ2
φ1
TC
φ2
φ1
TC
φ2
φ1
TI
φ2
φ1
TI
φ2
φ1
TI
φ2
φ1
TS
φ2
φ1
TC
φ2
φ1
TC
φ2
φ1
TS
φ2
φ1
INTA CYCLE 2
BUS CYCLE
CLK
S1
S0
M/IO,
LOCK
A23 - A0
BHE
D15 - D0
READY
INTA
MCE
ALE
DT/R
DEN
(SEE NOTE 21)
(SEE NOTE 22)
DON’T CARE
PREVIOUS
WRITE CYCLE
(SEE NOTE 18)
VECTOR
(SEE NOTE 20)
NOT READY READY
(SEE NOTE 19)
NOT READY
READY
COD/INTA
TYPE
80C286
82C288
80C286
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