參數(shù)資料
型號: IS80C286-20
廠商: Intersil
文件頁數(shù): 44/60頁
文件大?。?/td> 0K
描述: IC CPU 16BIT 5V 20MHZ 68-PLCC
標(biāo)準(zhǔn)包裝: 18
處理器類型: 80C286 16-位
速度: 20MHz
電壓: 5V
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 68-PLCC(24.23x24.23)
包裝: 管件
49
FIGURE 37. EXITING AND ENTERING HOLD
NOTES:
48. These signals may not be driven by the 80C286 during the time shown. The worst case in terms of latest float time is shown.
49. The data bus will be driven as shown if the cycle before TI in the diagram was a write TC.
50. The 80C286 puts its status pins in a high impedance logic one state during TH.
51. For HOLD request set up to HLDA, refer to Figure 29.
52. BHE and LOCK are driven at this time but will not become valid until TS.
53. The data bus will remain in a high impedance state if a read cycle is performed.
Waveforms (Continued)
TH
φ1
BUS
CYCLE TYPE
VCH
CLK
VCL
S1
S0
BHE, LOCK
80C28
6
φ2
HLDA
CLK
D15 - D0
PCLK
80
C284
A23 - A0,
M/IO,
COD/INTA
φ1
φ2
φ1
φ2
φ1
φ2
16
15
14
13
12A
12B
TS OR TI
TI
TH
(SEE NOTE 51)
(SEE NOTE 50)
(SEE NOTE 48)
(SEE NOTE 49)
(SEE NOTE 53)
(SEE NOTE 52)
(SEE NOTE 50)
IF TS
IF NPX TRANSFER
VALID
VALID IF WRITE
80C286
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