參數(shù)資料
型號(hào)： IS80C286-20
廠商： Intersil
文件頁(yè)數(shù)： 46/60頁(yè)
文件大?。?/td> 0K
描述： IC CPU 16BIT 5V 20MHZ 68-PLCC
標(biāo)準(zhǔn)包裝： 18
處理器類型： 80C286 16-位
速度： 20MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 68-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 68-PLCC（24.23x24.23）
包裝： 管件
50
ASSUMING WORD-ALIGNED MEMORY OPERAND. IF ODD ALIGNED, 80C286 TRANSFERS TO/FROM MEMORY BYTE-AT-A-TIME WITH TWO MEMORY
CYCLES.
FIGURE 38. 80C286 PEREQ/PEACK TIMING FOR ONE TRANSFER ONLY
NOTES:
54. PEACK always goes active during the first bus operation of a processor extension data operand transfer sequence. The first bus opera-
tion will be either a memory read at operand address or I/O read at port address 00FA(H).
55. To prevent a second processor extension data operand transfer, the worst case maximum time (Shown above) is
3 x
- 12AMAX -
MIN. The actual configuration dependent, maximum time is: 3 x
- 12AMAX -
MIN + N x 2 x
. N is the
number of extra TC states added to either the first or second bus operation of the processor extension data operand transfer sequence.
FIGURE 39. INITIAL 80C286 PIN STATE DURING RESET
NOTES:
56. Setup time for RESET
↑ may be violated with the consideration that φ1 of the processor clock may begin one system CLK period later.
57. Setup and hold times for RESET
↓ must be met for proper operation, but RESET ↓ may occur during φ1 or φ2.
58. The data bus is only guaranteed to be in a high impedance state at the time shown.
Waveforms (Continued)
1
12A
12B
4
5
TI
φ2
BUS
CYCLE TYPE
VCH
CLK
VCL
φ1
S1
S0
A23 - A0
M/IO,
PEACK
PEREQ
φ2
φ1
φ2
φ1
φ2
φ1
TS
TC
TS
TC
TI
I/O READ IF PROC. EXT. TO MEMORY
MEMORY READ IF MEMORY TO PROC. EXT.
MEMORY WRITE IF PROC. EXT. TO MEMORY
I/O WRITE IF MEMORY TO PROC. EXT.
MEMORY ADDRESS IF PROC. EXT. TO MEMORY TRANSFER I/O PORT
ADDRESS 00FA(H) IF MEMORY TO PROC. EXT. TRANSFER
I/O PORT ADDRESS 00FA(H) IF PROC. EXT. TO MEMORY TRANSFER
MEMORY ADDRESS IF MEMORY TO PROC. EXT. TRANSFER
(SEE NOTE 54)
(SEE NOTE 55)
COD INTA
1
4
1
4
1
6
7
12B
13
15
16
19
φ2
BUS
CYCLE TYPE
VCH
CLK
VCL
φ1
RESET
A23 - A0
(SEE NOTE 56)
φ2
φ1
φ2
φ1
φ2
φ1
φ2
UNKNOWN
S1
S0
BHE
M/IO
COD/INTA
LOCK
DATA
HLDA
PEACK
TX
TI
AT LEAST
(SEE NOTE 57)
(SEE NOTE 58)
16 CLK PERIODS
80C286
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