7 FN6667.5 December 13, 2011 FoutV Oscillator Stability vs Voltage 2.7V
參數(shù)資料
型號(hào)： ISL12020MIRZ-EVALZ
廠商： Intersil
文件頁(yè)數(shù)： 32/34頁(yè)
文件大小： 0K
描述： EVAL BOARD FOR ISL12020MIRZ
產(chǎn)品培訓(xùn)模塊： Solutions for Industrial Control Applications
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，實(shí)時(shí)時(shí)鐘（RTC）
嵌入式： 否
已用 IC / 零件： ISL12020M
主要屬性： 128 B SRAM，可編程夏令時(shí)
次要屬性： I²C 接口
已供物品： 板
ISL12020M
7
FN6667.5
December 13, 2011
FoutV
Oscillator Stability vs Voltage
2.7V
VDD 5.5V
-3
+3
ppm
Temperature Sensor Accuracy
VDD = VBAT = 3.3V
±2
°C
IRQ/FOUT (OPEN DRAIN OUTPUT)
VOL
Output Low Voltage
VDD = 5V, IOL = 3mA
0.4
V
VDD = 2.7V, IOL = 1mA
0.4
V
DC Operating Characteristics - RTC Test Conditions: VDD = +2.7 to +5.5V, TA= -40°C to +85°C,unlessotherwise stated. Boldface
limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 8)
TYP
(Note 9)
MAX
(Note 8)
UNITS
NOTES
Power-Down Timing Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated. Boldface limits apply
over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 8)
TYP
(Note 9)
MAX
(Note 8)
UNITS
NOTES
VDDSR-
VDD Negative Slew Rate
10
V/ms
VDDSR+
VDD Positive Slew Rate, Minimum
.05
V/ms
I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 8)
TYP (Note 9)
MAX
(Note 8)
UNITS
NOTES
VIL
SDA and SCL Input Buffer LOW
Voltage
-0.3
0.3 x VDD
V
VIH
SDA and SCL Input Buffer HIGH
Voltage
0.7 x VDD
VDD + 0.3
V
Hysteresis
SDA and SCL Input Buffer
Hysteresis
0.05 x VDD
VOL
SDA Output Buffer LOW Voltage,
Sinking 3mA
VDD = 5V, IOL = 3mA
0
0.02
0.4
V
CPIN
SDA and SCL Pin Capacitance
TA = +25°C, f = 1MHz, VDD =
5V, VIN =0V, VOUT = 0V
10
pF
fSCL
SCL Frequency
400
kHz
tIN
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the
max spec is suppressed.
50
ns
tAA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing
30% of VDD, until SDA exits
the 30% to 70% of VDD
window.
900
ns
tBUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VDD
during a STOP condition, to
SDA crossing 70% of VDD
during the following START
condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VDD
crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD
crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA
falling edge. Both crossing
70% of VDD.
600
ns
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