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參數(shù)資料
| 型號： | ISL76161AVZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONV D/A 12BIT HS 28-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 12 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 120mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 130M |
10
FN6720.2
December 23, 2013
recommended supply range is +3.0 to 3.6V (nominally +3.3V)
to maintain optimum SFDR. However, operation down to +2.7V
is possible with some degradation in SFDR. Reducing the
analog output current can help the SFDR at +2.7V. The SFDR
values stated in the “Electrical Specifications” table on page 4
were obtained with a +3.3V supply.
Ground Planes
Separate digital and analog ground planes should be used. All
of the digital functions of the device and their corresponding
components should be located over the digital ground plane
and terminated to the digital ground plane. The same is true
for the analog components and the analog ground plane.
Noise Reduction
To minimize power supply noise, 0.1
μF capacitors should be
placed as close as possible to the converter’s power supply
pins, AVDD and DVDD. Also, the layout should be designed
using separate digital and analog ground planes and these
capacitors should be terminated to the digital ground for
DVDD and to the analog ground for AVDD. Additional filtering
of the power supplies on the board is recommended.
Voltage Reference
The internal voltage reference of the device has a nominal
value of +1.23V with a
±40ppm/°C drift coefficient over the
full temperature range of the converter. It is recommended
that a 0.1
μF capacitor be placed as close as possible to the
REFIO pin, connected to the analog ground. The REFLO pin
(16) selects the reference. The internal reference can be
selected if pin 16 is tied low (ground). If an external
reference is desired, then pin 16 should be tied high (the
analog supply voltage) and the external reference driven into
REFIO, pin 17. The full scale output current of the converter
is a function of the voltage reference used and the value of
RSET. IOUT should be within the 2mA to 20mA range,
though operation below 2mA is possible, with performance
degradation.
If the internal reference is used, VFSADJ will equal
approximately 1.2V (pin 18). If an external reference is used,
VFSADJ will equal the external reference. The calculation for
IOUT (Full Scale) is:
If the full scale output current is set to approximately 20mA
by using the internal voltage reference (1.2V) and a 1.94k
Ω
RSET resistor, then the input coding to output current will
resemble those shown in Table 1.
Analog Output
IOUTA and IOUTB are complementary current outputs. The
sum of the two currents is always equal to the full scale
output current minus one LSB. If single ended use is
desired, a load resistor can be used to convert the output
current to a voltage. It is recommended that the unused
output be either grounded or equally terminated. The voltage
developed at the output must not violate the nominal output
voltage compliance range of -1.0V to 1.25V. ROUT (the
impedance loading each current output) should be chosen
so that the desired output voltage is produced in conjunction
with the output full scale current. If a known line impedance
is to be driven, then the output load resistor should be
chosen to match this impedance. The output voltage
equation is:
The most effective method for reducing the power
consumption is to reduce the analog output current, which
dominates the supply current. The maximum recommended
output current is 20mA.
Differential Output
IOUTA and IOUTB can be used in a differential-to-
single-ended arrangement to achieve better harmonic
rejection. With RDIFF = 50Ω and RLOAD = 50Ω, the circuit in
output of the transformer if the full scale output current of the
DAC is set to 20mA (used for the “Electrical Specifications”
were used for the “Typical Performance” curves on page 7.
The center tap in Figure 11 must be grounded.
In the circuit in Figure 12, the user is left with the option to
ground or float the center tap. The DC voltage that will exist
at either IOUTA or IOUTB if the center tap is floating is
IOUTDC x 2 x (RA//RB) V because RDIFF is DC shorted by
the transformer, and the DC currents from each output add
constructively. If the center tap is grounded, the DC voltage
is 0V. Recommended values for the circuit in Figure 12 are
RA = RB = 50Ω, RDIFF = 100Ω, assuming RLOAD = 50Ω. The
same, however leaving the center tap of Figure 12 floating
allows the circuit to find a more balanced virtual ground,
theoretically improving the even order harmonic rejection,
but likely reducing the signal swing available due to the
output voltage compliance range limitations.
TABLE 1. INPUT CODING vs. OUTPUT CURRENT WITH
INTERNAL REFERENCE AND RSET = 1.91kΩ
INPUT CODE (D11-D0)
IOUTA (mA)
IOUTB (mA)
11 11111 11111
20
0
10 00000 00000
10
00 00000 00000
0
20
I
OUT Full Scale
()
V
FSADJ R
SET
() 32
×
=
(EQ. 1)
V
OUT
I
OUT
R
OUT
×
=
(EQ. 2)
ISL76161
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