參數(shù)資料
型號: ISL76161AVZ-T
廠商: Intersil
文件頁數(shù): 3/12頁
文件大小: 0K
描述: IC CONV D/A 12BIT HS 28-TSSOP
標準包裝: 2,500
位數(shù): 12
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 120mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應商設(shè)備封裝: 28-TSSOP
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電流,單極
采樣率(每秒): 130M
11
FN6720.2
December 23, 2013
Propagation Delay
The converter requires two clock rising edges for data to be
represented at the output. Each rising edge of the clock
captures the present data word and outputs the previous
data. The propagation delay is therefore 1/CLK, plus <2ns of
settling. See Figure 13.
FIGURE 11. OUTPUT LOADING FOR DATASHEET
MEASUREMENTS
PIN 21
PIN 22
RDIFF
ISL76161
RLOAD
IOUTB
IOUTA
VOUT = (2 x IOUTA x REQ)V
LOAD SEEN BY THE TRANSFORMER
RLOAD REPRESENTS THE
1:1
REQ = 0.5 x (RLOAD // RDIFF)
AT EACH OUTPUT
FIGURE 12. ALTERNATIVE OUTPUT LOADING
PIN 21
PIN 22
ISL76161
IOUTB
IOUTA
VOUT = (2 x IOUTA x REQ)V
REQ = RA // [ 0.5 x (RLOAD // RDIFF) ], WHERE RA=RB
AT EACH OUTPUT
RLOAD
RDIFF
RA
RB
LOAD SEEN BY THE TRANSFORMER
RLOAD REPRESENTS THE
Timing Diagram
FIGURE 13. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
CLK
IOUT
50%
tPW1
tPW2
tSU
tHLD
tSU
tPD
tHLD
D11-D0
W0
W1
W2
W3
OUTPUT = W0
OUTPUT = W1
tPD
OUTPUT = W-1
ISL76161
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