參數(shù)資料
型號(hào): ISP1561BM
廠(chǎng)商: NXP SEMICONDUCTORS
元件分類(lèi): 總線(xiàn)控制器
英文描述: ISP1561BM
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁(yè)數(shù): 23/102頁(yè)
文件大?。?/td> 2875K
代理商: ISP1561BM
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
23 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Subsystem ID register (address: 2EH):
Subsystem ID values are vendor specific.
The bit description of the Subsystem ID register is given in
Table 19
.
[1]
X is 1H for OHCI1 and OHCI2; X is 2H for EHCI.
Expansion ROM Base Address register (address: 30H):
Some PCI devices,
especially those intended for use on expansion boards in the PC architecture, require
local EPROMs for expansion ROM. This four-byte register at offset 30H in a type 00H
predefined header is defined to handle the base address and size information for this
expansion ROM. The ISP1561 does not support expansion EPROM.
Capabilities Pointer register (address: 34H):
The Capabilities Pointer register is
used to point to a linked list of new capabilities implemented by the device. This
register is only valid if the CL bit in the Status register is set. If implemented, bit 1 and
bit 0 are reserved and should be set to 00B. Software should mask these bits off
before using this register as a pointer in Configuration Space to the first entry of a
linked list of new capabilities. The bit description of the register is given in
Table 20
.
Interrupt Line register (address: 3CH):
The Interrupt Line register is a one-byte
read/write register used to communicate interrupt line routing information. This
register must be implemented by any device (or device function) that uses an
interrupt pin. The interrupt allocation is done by the BIOS. The POST software needs
to write the routing information into this register as it initializes and configures the
system. The bit description of the Interrupt Line register is given in
Table 21
.
The value in this register tells which input of the system interrupt controller(s) the
interrupt pin of the device is connected to. The device itself does not use this value,
rather it is used by device drivers and operating systems. Device drivers and
operating systems can use this information to determine priority and vector
information. Values in this register are system architecture specific.
Table 18:
Bit
15 to 0
Subsystem Vendor ID register: bit description
Symbol
Access
SVID[15:0]
R
Value
1131H
Description
Subsystem Vendor ID
: 1131H is the subsystem Vendor ID
assigned to Philips Semiconductors.
Table 19:
Bit
15 to 0
Subsystem ID register: bit description
Symbol
Access
SID[15:0]
R
Value
156XH
[1]
Description
Subsystem ID
: For the ISP1561, Philips Semiconductors has
defined OHCI functions as 1561H, and the EHCI function as 1562H.
Table 20:
Bit
7 to 0
Capabilities Pointer register: bit description
Symbol
Access
CP[7:0]
R
Value
DCH
Description
Capabilities Pointer
: EHCI manages power efficiently using this
register. This Power Management register is allocated at offset
DCH. Only one Host Controller is needed to manage power in the
ISP1561.
Table 21:
Bit
7 to 0
Interrupt Line register: bit description
Symbol
Access
IL[7:0]
R/W
Value
00H
Description
Interrupt Line
: Indicates which IRQ is used for reporting interrupt
from the ISP1561.
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