參數(shù)資料
型號: ISP1561BM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: ISP1561BM
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁數(shù): 55/102頁
文件大小: 2875K
代理商: ISP1561BM
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
55 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
11.1.17
HcPeriodicStart register (address: value read from func0 or func1 of address
10H
+
40H)
The HcPeriodicStart register has a 14-bit programmable value that determines when
is the earliest time the Host Controller should start processing the periodic list. The bit
allocation is given in
Table 74
.
Table 73:
Bit
31 to 14
13 to 0
HcFmNumber register: bit description
Symbol
Description
-
reserved
FN[13:0]
FrameNumber
: This is incremented when HcFmRemaining is
re-loaded. It needs to be rolled over to 0H after FFFFH. When
entering the USBOPERATIONAL state, this is incremented
automatically. The content is written to HCCA after the Host
Controller has incremented FrameNumber at each frame
boundary and sent a SOF but before the Host Controller reads the
first ED in that frame. After writing to HCCA, the Host Controller
sets the SF (StartofFrame) in HcInterruptStatus.
Table 74:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcPeriodicStart register: bit allocation
31
30
29
28
27
26
25
24
reserved
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
23
22
21
20
19
18
17
16
reserved
0
-
0
-
0
-
0
-
0
-
0
-
0
-
9
0
-
8
15
14
13
12
11
10
reserved
P_S[13:8]
0
-
7
0
-
6
0
0
0
0
0
0
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
P_S[7:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 75:
Bit
31 to 14
13 to 0
HcPeriodicStart register: bit description
Symbol
Description
-
reserved
P_S[13:0]
PeriodicStart:
After a hardware reset, this field is cleared. This is
then set by the HCD during the Host Controller initialization. The
value is calculated roughly as 10% of the HcFmInterval. A typical
value is 3E67H. When HcFmRemaining reaches the value
specified, processing of the periodic lists have priority over
Control/Bulk processing. The Host Controller, therefore, starts
processing the Interrupt list after completing the current Control or
the Bulk transaction that is in progress.
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