參數(shù)資料
型號： ISP1561BM
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： ISP1561BM
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁數(shù)： 45/102頁
文件大?。?/td> 2875K
代理商： ISP1561BM
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
45 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
11.1.6
HcInterruptDisable register (address: value read from func0 or func1 of
address 10H
+
14H)
Each disable bit in the HcInterruptDisable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is
coupled with the HcInterruptEnable register. Therefore, writing logic 1 to a bit in this
register clears the corresponding bit in the HcInterruptEnable register, whereas
writing logic 0 to a bit in this register leaves the corresponding bit in the
HcInterruptEnable register unchanged. On a read, the current value of the
HcInterruptEnable register is returned. The register contains four bytes, and the bit
allocation is given in
Table 52
.
Bit
Symbol
Reset
Access
7
6
5
4
3
2
1
0
reserved
0
-
RHSC
0
R/W
FNO
0
R/W
UE
0
R/W
RD
0
R/W
SF
0
R/W
WDH
0
R/W
SO
0
R/W
Table 51:
Bit
31
HcInterruptEnable register: bit description
Symbol
Description
MIE
MasterInterruptEnable
: Logic 0 is ignored by the Host Controller.
Logic 1 enables interrupt generation by events specified in other
bits of this register.
OC
0 —
ignore
30
1 —
enable interrupt generation due to Ownership Change
reserved
0 —
ignore
29 to 7
6
-
RHSC
1 —
enable interrupt generation due to Root Hub Status Change
0 —
ignore
5
FNO
1 —
enable interrupt generation due to Frame Number Overflow
0 —
ignore
4
UE
1 —
enable interrupt generation due to Unrecoverable Error
0 —
ignore
3
RD
1 —
enable interrupt generation due to Resume Detect
0 —
ignore
2
SF
1 —
enable interrupt generation due to Start-of-Frame
0 —
ignore
1
WDH
1 —
enable interrupt generation due to HcDoneHead Writeback
0 —
ignore
0
SO
1 —
enable interrupt generation due to Scheduling Overrun
Table 52:
Bit
Symbol
Reset
Access
HcInterruptDisable register: bit allocation
31
30
MIE
OC
0
0
R/W
R/W
29
28
27
26
25
24
reserved
0
-
0
-
0
-
0
-
0
-
0
-
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1561BM,518 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1561BM,551 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1561BM,557 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1561BMGA 功能描述:IC USB HOST CTRL HI-SPD 128LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
ISP1561BMGE 功能描述:IC USB PCI HOST CTRLR 128-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
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