參數(shù)資料
型號： ISP1760BE
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-425-1, LQFP-128
文件頁數(shù)： 32/105頁
文件大?。?/td> 449K
代理商： ISP1760BE
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
32 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
[1]
The reserved bits should always be written with the reset value.
[1]
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal
Serial Bus Rev. 1.0
8.2.3
USBINTR register (R/W: 0028h)
The USB Interrupt Enable (USBINTR) register enables and disables reporting of the
corresponding interrupt to the software. When a bit is set and the corresponding interrupt
is active, an interrupt is generated to the host. Interrupt sources that are disabled in this
register still appear in USBSTS to allow the software to poll for events. The USBINTR
register bit allocation is given in
Table 16
.
Table 14:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
USBSTS register: bit allocation
31
30
29
28
27
26
25
24
reserved
[1]
0
0
0
0
0
0
0
0
R/W
23
R/W
22
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
reserved
[1]
0
0
0
0
0
0
0
0
R/W
15
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
reserved
[1]
0
0
0
1
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
FLR
0
R/W
R/W
2
PCD
0
R/W
R/W
1
R/W
0
reserved
[1]
reserved
[1]
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Table 15:
Bit
31 to 4 -
3
USBSTS register: bit description
Symbol Description
[1]
reserved; write logic 0
FLR
Frame List Rollover
: The Host Controller sets this bit to logic 1 when the
Frame List Index rolls over from its maximum value to zero.
PCD
Port Change Detect
: The Host Controller sets this bit to logic 1 when any port,
where the PO bit is cleared, has a change to a one or a FPR bit changes to a
one as a result of a J-K transition detected on a suspended port.
-
reserved
2
1 to 0
Table 16:
Bit
Symbol
Reset
Access
USBINTR register: bit allocation
31
30
29
28
27
26
25
24
reserved
[1]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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