參數(shù)資料
型號(hào)： ISP1760BE
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-425-1, LQFP-128
文件頁(yè)數(shù)： 71/105頁(yè)
文件大小： 449K
代理商： ISP1760BE
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
71 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
Table 71:
Bit
DW7
63 to 32
DW6
31 to 0
DW5
63 to 32
DW4
31 to 6
5
Start and complete split for bulk, QHASS/SC: bit description
Symbol
Access
Description
reserved
-
-
reserved
-
-
reserved
-
-
reserved
J
-
SW —
writes
-
0 —
To increment the PTD pointer
1 —
To enable the next PTD branching.
Next PTD branching assigned by the PTD pointer.
4 to 0
NextPTDPointer
[1:0]
SW —
writes
DW3
63
A
SW —
sets
HW —
resets
HW —
writes
HW —
writes
Active
: Write the same value as that in V.
62
61
H
B
Halt
: This bit correspond to the Halt bit of the Status field of QH.
Babble
: This bit correspond to the Babble Detected bit in the Status
field of the iTD, SiTD or QH.
1 —
when babbling is detected, A and V are set to 0.
Transaction Error
: This bit corresponds to the Transaction Error bit in
the status field.
Start/Complete
:
0 —
Start split
1 —
Complete split.
-
Data Toggle
: Set the Data Toggle bit to start for the PTD.
60
X
59
SC
SW —
writes 0
HW —
updates
58
57
reserved
DT
-
HW —
writes
SW —
writes
HW —
updates
SW —
writes
56 to 55
Cerr[1:0]
Error Counter
: This field contains the error count for start and complete
split (QHASS). When an error has no response or bad response,
Cerr[1:0] will be decremented to zero and then Valid will be set to zero.
A NAK or NYET will reset Cerr[1:0]. For details, refer to Enhanced Host
Controller Interface Specification for Universal Serial Bus Rev. 1.0
Section 4.12.1.2
If retry has insufficient time at the beginning of a new SOF, the first PTD
must be this retry. This can be accomplished by if aperiodic PTD is not
advanced.
NAK Counter
. The V bit is reset if NakCnt decrements to zero and RL
is a non-zero value. Not applicable to isochronous split transactions.
54 to 51
NakCnt[3:0]
HW —
writes
SW —
writes
-
HW —
writes
50 to 47
46 to 32
reserved
NrBytesTransferred
[14:0]
-
Number of Bytes Transferred
: This field indicates the number of bytes
sent or received for this transaction.
DW2
31 to 29
reserved
-
-
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ISP1760BE,518 功能描述:輸入/輸出控制器接口集成電路 USB HOST CONTROLLER RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
ISP1760BE,551 功能描述:輸入/輸出控制器接口集成電路 USB HS HOST CONTRLLR RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
ISP1760BE,557 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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