參數(shù)資料
型號(hào)： ISP1760BE
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-425-1, LQFP-128
文件頁數(shù)： 46/105頁
文件大?。?/td> 449K
代理商： ISP1760BE
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
46 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
8.3.10
DMA Start Address register (W: 0344h)
This register defines the start address select for the DMA read and write operations. See
Table 48
for the bit allocation.
[1]
The reserved bits should always be written with the reset value.
8.3.11
Power Down Control register (R/W: 0354h)
This register is used to turn off power to the internal blocks of the ISP1760 to obtain
maximum power savings.
Table 50
shows the bit allocation of the register.
Table 47:
Bit
31 to 24
Edge Interrupt Count register: bit description
Symbol
Description
MIN_
WIDTH[7:0]
interrupts in
μ
SOFs (1
μ
SOF = 125
μ
s). This is not valid for level
interrupts. A count of zero means that interrupts occur as and when an
event occurs.
-
reserved
NO_OF_
CLK[15:0]
must be kept asserted on the interface. The default IRQ pulse width is
approximately 500 ns.
Minimum Width
: Indicates the minimum width between two edge
23 to 16
15 to 0
Number of Clocks
: Count in number of clocks that the edge interrupt
Table 48:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
DMA Start Address register: bit allocation
31
30
29
28
27
26
25
24
reserved
[1]
0
W
23
0
W
22
0
W
21
0
W
20
0
W
19
0
W
18
0
W
17
0
W
16
reserved
[1]
0
W
15
0
W
14
0
W
13
0
W
12
0
W
11
0
W
10
0
W
9
0
W
8
START_ADDR_DMA[15:8]
0
W
4
START_ADDR_DMA[7:0]
0
W
0
W
7
0
W
6
0
W
5
0
W
3
0
W
2
0
W
1
0
W
0
0
W
0
W
0
W
0
W
0
W
0
W
0
W
Table 49:
Bit
31 to 16
15 to 0
DMA Start Address register: bit description
Symbol
Description
-
reserved
START_ADDR
_DMA[15:0]
cycles.
Start Address for DMA
: The start address for DMA read or write
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