參數(shù)資料
型號： ISP1760BE
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-425-1, LQFP-128
文件頁數(shù)： 44/105頁
文件大?。?/td> 449K
代理商： ISP1760BE
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
44 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
8.3.7
ATL Done Timeout register (R/W: 0338h)
The bit description of the ATL Done Timeout register is given in
Table 43
.
8.3.8
Memory register (R/W: 033Ch)
The Memory register contains the base memory read address and the respective bank.
This register needs to be set only before a first memory read cycle. Once written, the
address will be latched for the bank and will be incremented for every read of that bank,
until a new address for that bank is written to change the address pointer.
The bit description of the register is given in
Table 44
.
Table 42:
Bit
31 to 3
2
Buffer Status register: bit description
Symbol
Description
-
reserved
ISO_BUF_
FILL
1 —
Indicates one of the ISO PTDs is filled, and the ISO PTD area will
be processed
0 —
Indicates there is no PTD in this area. Therefore, processing of
the ISO PTDs will be completely skipped.
INT_BUF_
FILL
1 —
Indicates one of the INT PTDs is filled, and the INT PTD area will
be processed
0 —
Indicates there is no PTD in this area. Therefore, processing of
the INT PTDs will be completely skipped.
ATL_BUF_
FILL
1 —
Indicates one of the ATL PTDs is filled, and the ATL PTD area will
be processed
0 —
Indicates there is no PTD in this area. Therefore, processing of
the ATL PTDs will be completely skipped.
ISO Buffer Filled
:
1
INT Buffer Filled
:
0
ATL Buffer Filled
:
Table 43:
Bit
31 to 0
ATL Done Timeout register: bit description
Symbol
Access
ATL_DONE
_TIMEOUT
[31:0]
Value
0000 0000h
ATL Done Timeout
: This register determines the
ATL done timeout interrupt. This register defines
the timeout in ms after which the ISP1760 asserts
the INT line, if enabled. It is applicable to the ATL
done PTDs only.
Description
R/W
Table 44:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Memory register: bit allocation
31
30
29
28
27
26
25
24
reserved
[1]
0
0
0
0
0
0
0
0
R/W
23
R/W
22
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
reserved
[1]
MEM_BANK_SEL[1:0]
0
R/W
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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ISP1760BE,518 功能描述:輸入/輸出控制器接口集成電路 USB HOST CONTROLLER RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
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