參數(shù)資料
型號： K4T1G044QC-ZCLE6
元件分類： DRAM
英文描述： 256M X 4 DDR DRAM, 0.45 ns, PBGA60
封裝： ROHS COMPLIANT, FBGA-60
文件頁數(shù)： 15/26頁
文件大?。?/td> 487K
代理商： K4T1G044QC-ZCLE6
DDR2 SDRAM
K4T1G044QC
K4T1G084QC
Rev. 1.1 June 2007
22 of 26
9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing.
tXARDS is expected to be used for slow active power down exit timing.
10. AL = Additive Latency
11. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and tRAS(min) have been satisfied.
12. For DDR2-533/400, A minimum of two clocks (2*tCK) is required irrespective of operating frequency.
For DDR2-800/667, tnPARAM=RU{tPARAM / tCK(avg)}, which is in clock cycles, assuming all input clock jitter specification are satisfied.
13. Timings are guaranteed with command/address input slew rate of 1.0 V/ns.
14. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester
correlation.
15. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0 V/ns.
16. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns
in differential strobe mode and a slew rate of 1V/ns in single ended mode.
17. tDS and tDH derating Values
For all input signals the total tDS (setup time) and tDH(hold time) required is calculated by adding the datasheet tDS(base) and tDH(base) value to the
delta tDS and delta tDH derating value respectively. Example: tDS(total setup time)= tDS(base) + delta tDS.
tDS, tDH Derating Values of DDR2-400, DDR2-533 (ALL units in ‘ps’, Note 1 applies to entire Table)
DQS,DQS Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
0.8V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
DQ
Siew
rate
V/ns
2.0
125
45
125
45
125
45
-
1.5
832183
218321
9533
-
1.0
0
12
24
-
0.9
-
-11
-14
-11
-14
1
-2
13
10
25
22
-
0.8
-
-25
-31
-13
-19
-1
-7
11
5
23
17
-
0.7
-
-31
-42
-19
-30
-7
-18
5
-6
17
6
-
0.6
-
-43
-59
-31
-47
-19
-35
-7
-23
5
-11
0.5
-
-74
-89
-62
-77
-50
-65
-38
-53
0.4
-
-127
-140
-115
-128
-103
-116
tDS, tDH Derating Values for DDR2-667, DDR2-800 (ALL units in ‘ps’, Note 1 applies to entire Table)
DQS,DQS Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
0.8V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
DQ
Slew
rate
V/ns
2.0
100
45
100
45
100
45
-
1.5
6721672167217933
-
1.0
000000
12
24
-
0.9
-
-5
-14
-5
-14
7
-2
19
10
31
22
-
0.8
-
-13
-31
-1
-19
11
-7
23
5
35
17
-
0.7
-
-----
-10
-42
2
-30
14
-18
26
-6
38
6
--
0.6
-
-------
-10
-59
2
-47
14
-35
26
-23
38
-11
0.5
-
---------
-24
-89
-12
-77
0
-65
12
-53
0.4
-
-----------
-52
-140
-40
-128
-28
-116
15.0 Specific Notes for dedicated AC parameters
相關(guān)PDF資料
PDF描述
K4T56163QI-ZLD50 16M X 16 SYNCHRONOUS DRAM, 0.5 ns, PBGA84
K5A3240YT Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM
K6R1004C1C 256Kx4 Bit (with OE) High-Speed CMOS Static RAM(5.0V Operating).
K6R1004C1C-I 256Kx4 Bit (with OE) High-Speed CMOS Static RAM(5.0V Operating).
K6R1004C1C-I10 256Kx4 Bit (with OE) High-Speed CMOS Static RAM(5.0V Operating).
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4T1G044QE 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb E-die DDR2 SDRAM
K4T1G044QE-HCLE6 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb E-die DDR2 SDRAM
K4T1G044QE-HCLE7 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb E-die DDR2 SDRAM
K4T1G044QE-HCLF7 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb E-die DDR2 SDRAM
K4T1G044QF 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb F-die DDR2 SDRAM
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