參數(shù)資料
型號(hào): K4T1G044QC-ZCLE6
元件分類: DRAM
英文描述: 256M X 4 DDR DRAM, 0.45 ns, PBGA60
封裝: ROHS COMPLIANT, FBGA-60
文件頁(yè)數(shù): 21/26頁(yè)
文件大?。?/td> 487K
代理商: K4T1G044QC-ZCLE6
DDR2 SDRAM
K4T1G044QC
K4T1G084QC
Rev. 1.1 June 2007
4 of 26
Note :
1. Speed bin is in order of CL-tRCD-tRP.
2. RoHS Compliant.
Organization
DDR2-800 6-6-6
DDR2-667 5-5-5
DDR2-533 4-4-4
DDR2-400 3-3-3
Package
256Mx4
K4T1G044QC-ZC(L)F7
K4T1G044QC-ZC(L)E6
K4T1G044QC-ZC(L)D5
K4T1G044QC-ZC(L)CC
60 FBGA
128Mx8
K4T1G084QC-ZC(L)F7
K4T1G084QC-ZC(L)E6
K4T1G084QC-ZC(L)D5
K4T1G084QC-ZC(L)CC
60 FBGA
JEDEC standard 1.8V ± 0.1V Power Supply
VDDQ = 1.8V ± 0.1V
200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/
pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/
sec/pin
8 Banks
Posted CAS
Programmable CAS Latency: 3, 4, 5, 6
Programmable Additive Latency: 0, 1, 2, 3, 4, 5
Write Latency(WL) = Read Latency(RL) -1
Burst Length: 4 , 8(Interleave/nibble sequential)
Programmable Sequential / Interleave Burst Mode
Bi-directional Differential Data-Strobe (Single-ended data-
strobe is an optional feature)
Off-Chip Driver(OCD) Impedance Adjustment
On Die Termination
Special Function Support
- PASR(Partial Array Self Refresh)
- 50ohm ODT
- High Temperature Self-Refresh rate enable
Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85
°C < TCASE < 95 °C
All of Lead-free products are compliant for RoHS
The 1Gb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 8
banks device. This synchronous device achieves high speed dou-
ble-data-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for
general applications.
The chip is designed to comply with the following key DDR2
SDRAM features such as posted CAS with additive latency, write
latency = read latency - 1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair
of externally supplied differential clocks. Inputs are latched at the
crosspoint of differential clocks (CK rising and CK falling). All I/Os
are synchronized with a pair of bidirectional strobes (DQS and
DQS) in a source synchronous fashion. The address bus is used
to convey row, column, and bank address information in a RAS/
CAS multiplexing style. For example, 1Gb(x4) device receive 14/
11/3 addressing.
The 1Gb DDR2 device operates with a single 1.8V ± 0.1V power
supply and 1.8V ± 0.1V VDDQ.
The 1Gb DDR2 device is available in 60ball FBGAs(x4/x8)
Note : The functionality described and the timing specifications included in
this data sheet are for the DLL Enabled mode of operation.
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device
Operation & Timing Diagram”.
1.0 Ordering Information
Speed
DDR2-800 6-6-6
DDR2-667 5-5-5
DDR2-533 4-4-4
DDR2-400 3-3-3
Units
CAS Latency
6
5
43
tCK
tRCD(min)
15
ns
tRP(min)
15
ns
tRC(min)
60
55
ns
2.0 Key Features
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